| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_stream_encoder.c | 1595 int tg_inst, bool enable)
1598 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1604 int tg_inst)
1608 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1614 uint32_t tg_inst = 0; local in function:dig_source_otg
1617 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1619 return tg_inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_stream_encoder.c | 1532 int tg_inst, bool enable)
1535 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1541 int tg_inst)
1545 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1551 uint32_t tg_inst = 0; local in function:enc1_dig_source_otg
1554 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1556 return tg_inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 1055 unsigned int i, enc_inst, tg_inst = 0; local in function:dc_validate_seamless_boot_timing
1076 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1082 // tg_inst not found
1086 if (tg_inst >= dc->res_pool->timing_generator_count)
1089 tg = dc->res_pool->timing_generators[tg_inst];
1138 tg_inst, &pix_clk_100hz);
|
| amdgpu_dc_resource.c | 1888 unsigned int i, inst, tg_inst = 0; local in function:acquire_resource_from_hw_enabled_state
1901 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
1907 // tg_inst not found
1911 if (tg_inst >= pool->timing_generator_count)
1914 if (!res_ctx->pipe_ctx[tg_inst].stream) {
1915 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
1917 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
1918 pipe_ctx->plane_res.mi = pool->mis[tg_inst];
1919 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
1920 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
[all...] |
