| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| priv.h | 23 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member in struct:nvkm_gr_func
|
| gf100.h | 127 u8 tile[TPC_MAX]; member in struct:gf100_gr
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/ |
| engine.h | 27 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member in struct:nvkm_engine_func
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| priv.h | 34 } tile; member in struct:nvkm_fb_func
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_bo.h | 43 struct nouveau_drm_tile *tile; member in struct:nouveau_bo
|
| nouveau_drv.h | 195 } tile; member in struct:nouveau_drm
|
| nouveau_bo.c | 61 int i = reg - drm->tile.reg;
63 struct nvkm_fb_tile *tile = &fb->tile.region[i]; local in function:nv10_bo_update_tile_region
67 if (tile->pitch)
68 nvkm_fb_tile_fini(fb, i, tile);
71 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
73 nvkm_fb_tile_prog(fb, i, tile);
80 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; local in function:nv10_bo_get_tile_region
82 spin_lock(&drm->tile.lock)
114 struct nouveau_drm_tile *tile, *found = NULL; local in function:nv10_bo_set_tiling
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_mman.c | 24 struct tile { struct
38 static u64 tiled_offset(const struct tile *tile, u64 v)
42 if (tile->tiling == I915_TILING_NONE)
45 y = div64_u64_rem(v, tile->stride, &x);
46 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
48 if (tile->tiling == I915_TILING_X) {
49 v += y * tile->width
340 struct tile tile; local in function:igt_partial_tiling
358 struct tile tile; local in function:igt_partial_tiling
477 struct tile tile; local in function:igt_smoke_tiling
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| fb.h | 46 } tile; member in struct:nvkm_fb
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_connector.c | 975 * TILE:
976 * Connector tile group property to indicate how a set of DRM connector
1212 "TILE", 0);
1851 * drm_connector_set_path_property - set tile property on connector
1880 * drm_connector_set_tile_property - set tile property on connector
1883 * This looks up the tile information for a connector, and creates a
1895 char tile[256]; local in function:drm_connector_set_tile_property
1908 snprintf(tile, 256, "%d:%d:%d:%d:%d:%d:%d:%d",
1916 strlen(tile) + 1,
1917 tile,
[all...] |
| drm_edid.c | 5705 const struct displayid_tiled_block *tile = (const struct displayid_tiled_block *)block; local in function:drm_parse_tiled_block
5711 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5712 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5714 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5715 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5716 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v7_0.c | 1038 uint32_t *tile, *macrotile; local in function:gfx_v7_0_tiling_mode_table_init
1040 tile = adev->gfx.config.tile_mode_array;
1057 tile[reg_offset] = 0;
1063 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1079 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si.c | 2502 u32 *tile = rdev->config.si.tile_mode_array; local in function:si_tiling_mode_table_init
2521 tile[reg_offset] = 0;
2527 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2536 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2545 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2554 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2562 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2563 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2572 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2581 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)
[all...] |
| radeon_cik.c | 2348 u32 *tile = rdev->config.cik.tile_mode_array; local in function:cik_tiling_mode_table_init
2377 tile[reg_offset] = 0;
2383 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2387 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2391 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2395 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2399 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2403 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2406 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2410 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| cmd_parser.c | 1327 u32 stride, tile; local in function:gen8_check_mi_display_flip
1334 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1339 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1345 if (tile != info->tile_val)
1346 gvt_dbg_cmd("cannot change tile during async flip\n");
|
