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      1 /*	$NetBSD: smu8_smumgr.h,v 1.2 2021/12/18 23:45:27 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2015 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef _SMU8_SMUMGR_H_
     26 #define _SMU8_SMUMGR_H_
     27 
     28 
     29 #define MAX_NUM_FIRMWARE                        8
     30 #define MAX_NUM_SCRATCH                         11
     31 #define SMU8_SCRATCH_SIZE_NONGFX_CLOCKGATING      1024
     32 #define SMU8_SCRATCH_SIZE_NONGFX_GOLDENSETTING    2048
     33 #define SMU8_SCRATCH_SIZE_SDMA_METADATA           1024
     34 #define SMU8_SCRATCH_SIZE_IH                      ((2*256+1)*4)
     35 
     36 #define SMU_EnabledFeatureScoreboard_SclkDpmOn    0x00200000
     37 
     38 enum smu8_scratch_entry {
     39 	SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
     40 	SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1,
     41 	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE,
     42 	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
     43 	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME,
     44 	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
     45 	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
     46 	SMU8_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
     47 	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G,
     48 	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
     49 	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
     50 	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
     51 	SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
     52 	SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
     53 	SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
     54 	SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
     55 	SMU8_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
     56 	SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
     57 	SMU8_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
     58 	SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_START,
     59 	SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
     60 	SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
     61 };
     62 
     63 struct smu8_buffer_entry {
     64 	uint32_t data_size;
     65 	uint64_t mc_addr;
     66 	void *kaddr;
     67 	enum smu8_scratch_entry firmware_ID;
     68 	struct amdgpu_bo *handle; /* as bo handle used when release bo */
     69 };
     70 
     71 struct smu8_register_index_data_pair {
     72 	uint32_t offset;
     73 	uint32_t value;
     74 };
     75 
     76 struct smu8_ih_meta_data {
     77 	uint32_t command;
     78 	struct smu8_register_index_data_pair register_index_value_pair[1];
     79 };
     80 
     81 struct smu8_smumgr {
     82 	uint8_t driver_buffer_length;
     83 	uint8_t scratch_buffer_length;
     84 	uint16_t toc_entry_used_count;
     85 	uint16_t toc_entry_initialize_index;
     86 	uint16_t toc_entry_power_profiling_index;
     87 	uint16_t toc_entry_aram;
     88 	uint16_t toc_entry_ih_register_restore_task_index;
     89 	uint16_t toc_entry_clock_table;
     90 	uint16_t ih_register_restore_task_size;
     91 	uint16_t smu_buffer_used_bytes;
     92 
     93 	struct smu8_buffer_entry toc_buffer;
     94 	struct smu8_buffer_entry smu_buffer;
     95 	struct smu8_buffer_entry firmware_buffer;
     96 	struct smu8_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
     97 	struct smu8_buffer_entry meta_data_buffer[MAX_NUM_FIRMWARE];
     98 	struct smu8_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
     99 };
    100 
    101 #endif
    102