| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/ |
| mt8167.dtsi | 20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
52 clocks = <&topckgen CLK_TOP_SMI_MM>;
60 clocks = <&topckgen CLK_TOP_SMI_MM>,
61 <&topckgen CLK_TOP_RG_VDEC>;
68 clocks = <&topckgen CLK_TOP_SMI_MM>;
75 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
76 <&topckgen CLK_TOP_RG_SLOW_MFG>;
|
| mt6779.dtsi | 150 topckgen: clock-controller@10000000 { label
151 compatible = "mediatek,mt6779-topckgen", "syscon";
|
| mt6797.dtsi | 114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
|
| mt8516.dtsi | 58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>
[all...] |
| mt7622.dtsi | 243 clocks = <&topckgen CLK_TOP_HIF_SEL>;
252 <&topckgen CLK_TOP_AXI_SEL>;
285 topckgen: topckgen@10210000 { label
286 compatible = "mediatek,mt7622-topckgen",
325 clocks = <&topckgen CLK_TOP_RTC>;
389 clocks = <&topckgen CLK_TOP_UART_SEL>,
400 clocks = <&topckgen CLK_TOP_UART_SEL>,
411 clocks = <&topckgen CLK_TOP_UART_SEL>,
422 clocks = <&topckgen CLK_TOP_UART_SEL>
[all...] |
| mt2712e.dtsi | 90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>
[all...] |
| mt8183.dtsi | 370 topckgen: syscon@10000000 { label
371 compatible = "mediatek,mt8183-topckgen", "syscon";
428 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
443 clocks = <&topckgen CLK_TOP_MUX_MFG>;
475 clocks = <&topckgen CLK_TOP_MUX_MM>,
497 clocks = <&topckgen CLK_TOP_MUX_CAM>,
515 clocks = <&topckgen CLK_TOP_MUX_IMG>,
538 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
539 <&topckgen CLK_TOP_MUX_DSP>,
556 clocks = <&topckgen CLK_TOP_MUX_DSP1>
[all...] |
| mt8173.dtsi | 356 topckgen: clock-controller@10000000 { label
357 compatible = "mediatek,mt8173-topckgen";
468 clocks = <&topckgen CLK_TOP_MM_SEL>;
474 clocks = <&topckgen CLK_TOP_MM_SEL>,
475 <&topckgen CLK_TOP_VENC_SEL>;
481 clocks = <&topckgen CLK_TOP_MM_SEL>;
487 clocks = <&topckgen CLK_TOP_MM_SEL>;
494 clocks = <&topckgen CLK_TOP_MM_SEL>,
495 <&topckgen CLK_TOP_VENC_LT_SEL>;
543 <&topckgen CLK_TOP_RTC_SEL>
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| mt8135.dtsi | 127 topckgen: topckgen@10000000 { label
128 compatible = "mediatek,mt8135-topckgen";
|
| mt2701.dtsi | 126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI0_SEL>,
390 <&topckgen CLK_TOP_FLASH_SEL>;
403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
404 <&topckgen CLK_TOP_SPI1_SEL>
[all...] |
| mt7629.dtsi | 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
138 topckgen: syscon@10210000 { label
139 compatible = "mediatek,mt7629-topckgen", "syscon";
216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
248 clocks = <&topckgen CLK_TOP_PWM_SEL>,
252 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>
[all...] |
| mt7623.dtsi | 226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
424 clocks = <&topckgen CLK_TOP_PWM_SEL>,
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
553 <&topckgen CLK_TOP_FLASH_SEL>
[all...] |
