1 /* $NetBSD: dce_i2c_hw.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DCE_I2C_HW_H__ 29 #define __DCE_I2C_HW_H__ 30 31 enum dc_i2c_status { 32 DC_I2C_STATUS__DC_I2C_STATUS_IDLE, 33 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW, 34 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW, 35 DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY = 2, 36 }; 37 38 enum dc_i2c_arbitration { 39 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL, 40 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH 41 }; 42 43 enum i2c_channel_operation_result { 44 I2C_CHANNEL_OPERATION_SUCCEEDED, 45 I2C_CHANNEL_OPERATION_FAILED, 46 I2C_CHANNEL_OPERATION_NOT_GRANTED, 47 I2C_CHANNEL_OPERATION_IS_BUSY, 48 I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED, 49 I2C_CHANNEL_OPERATION_CHANNEL_IN_USE, 50 I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED, 51 I2C_CHANNEL_OPERATION_ENGINE_BUSY, 52 I2C_CHANNEL_OPERATION_TIMEOUT, 53 I2C_CHANNEL_OPERATION_NO_RESPONSE, 54 I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS, 55 I2C_CHANNEL_OPERATION_WRONG_PARAMETER, 56 I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES, 57 I2C_CHANNEL_OPERATION_NOT_STARTED 58 }; 59 60 61 enum dce_i2c_transaction_action { 62 DCE_I2C_TRANSACTION_ACTION_I2C_WRITE = 0x00, 63 DCE_I2C_TRANSACTION_ACTION_I2C_READ = 0x10, 64 DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20, 65 66 DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40, 67 DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT = 0x50, 68 DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60, 69 70 DCE_I2C_TRANSACTION_ACTION_DP_WRITE = 0x80, 71 DCE_I2C_TRANSACTION_ACTION_DP_READ = 0x90 72 }; 73 74 enum { 75 I2C_SETUP_TIME_LIMIT_DCE = 255, 76 I2C_SETUP_TIME_LIMIT_DCN = 3, 77 I2C_HW_BUFFER_SIZE_DCE100 = 538, 78 I2C_HW_BUFFER_SIZE_DCE = 144, 79 I2C_SEND_RESET_LENGTH_9 = 9, 80 I2C_SEND_RESET_LENGTH_10 = 10, 81 DEFAULT_I2C_HW_SPEED = 50, 82 DEFAULT_I2C_HW_SPEED_100KHZ = 100, 83 TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32, 84 }; 85 86 #define I2C_HW_ENGINE_COMMON_REG_LIST(id)\ 87 SRI(SETUP, DC_I2C_DDC, id),\ 88 SRI(SPEED, DC_I2C_DDC, id),\ 89 SRI(HW_STATUS, DC_I2C_DDC, id),\ 90 SR(DC_I2C_ARBITRATION),\ 91 SR(DC_I2C_CONTROL),\ 92 SR(DC_I2C_SW_STATUS),\ 93 SR(DC_I2C_TRANSACTION0),\ 94 SR(DC_I2C_TRANSACTION1),\ 95 SR(DC_I2C_TRANSACTION2),\ 96 SR(DC_I2C_TRANSACTION3),\ 97 SR(DC_I2C_DATA),\ 98 SR(MICROSECOND_TIME_BASE_DIV) 99 100 #define I2C_SF(reg_name, field_name, post_fix)\ 101 .field_name = reg_name ## __ ## field_name ## post_fix 102 103 #define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 104 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 105 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\ 106 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\ 107 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\ 108 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\ 109 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\ 110 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\ 111 I2C_SF(DC_I2C_DDC1_HW_STATUS, DC_I2C_DDC1_HW_STATUS, mask_sh),\ 112 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, mask_sh),\ 113 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\ 114 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\ 115 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\ 116 I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\ 117 I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\ 118 I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\ 119 I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\ 120 I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\ 121 I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\ 122 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\ 123 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\ 124 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\ 125 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\ 126 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\ 127 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\ 128 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\ 129 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\ 130 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\ 131 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\ 132 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\ 133 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\ 134 I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\ 135 I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\ 136 I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\ 137 I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\ 138 I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\ 139 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh) 140 141 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ 142 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 143 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh) 144 145 struct dce_i2c_shift { 146 uint8_t DC_I2C_DDC1_ENABLE; 147 uint8_t DC_I2C_DDC1_TIME_LIMIT; 148 uint8_t DC_I2C_DDC1_DATA_DRIVE_EN; 149 uint8_t DC_I2C_DDC1_CLK_DRIVE_EN; 150 uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL; 151 uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; 152 uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY; 153 uint8_t DC_I2C_DDC1_HW_STATUS; 154 uint8_t DC_I2C_SW_DONE_USING_I2C_REG; 155 uint8_t DC_I2C_SW_USE_I2C_REG_REQ; 156 uint8_t DC_I2C_NO_QUEUED_SW_GO; 157 uint8_t DC_I2C_SW_PRIORITY; 158 uint8_t DC_I2C_SOFT_RESET; 159 uint8_t DC_I2C_SW_STATUS_RESET; 160 uint8_t DC_I2C_GO; 161 uint8_t DC_I2C_SEND_RESET; 162 uint8_t DC_I2C_TRANSACTION_COUNT; 163 uint8_t DC_I2C_DDC_SELECT; 164 uint8_t DC_I2C_DDC1_PRESCALE; 165 uint8_t DC_I2C_DDC1_THRESHOLD; 166 uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; 167 uint8_t DC_I2C_SW_STOPPED_ON_NACK; 168 uint8_t DC_I2C_SW_TIMEOUT; 169 uint8_t DC_I2C_SW_ABORTED; 170 uint8_t DC_I2C_SW_DONE; 171 uint8_t DC_I2C_SW_STATUS; 172 uint8_t DC_I2C_STOP_ON_NACK0; 173 uint8_t DC_I2C_START0; 174 uint8_t DC_I2C_RW0; 175 uint8_t DC_I2C_STOP0; 176 uint8_t DC_I2C_COUNT0; 177 uint8_t DC_I2C_DATA_RW; 178 uint8_t DC_I2C_DATA; 179 uint8_t DC_I2C_INDEX; 180 uint8_t DC_I2C_INDEX_WRITE; 181 uint8_t XTAL_REF_DIV; 182 uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH; 183 uint8_t DC_I2C_REG_RW_CNTL_STATUS; 184 }; 185 186 struct dce_i2c_mask { 187 uint32_t DC_I2C_DDC1_ENABLE; 188 uint32_t DC_I2C_DDC1_TIME_LIMIT; 189 uint32_t DC_I2C_DDC1_DATA_DRIVE_EN; 190 uint32_t DC_I2C_DDC1_CLK_DRIVE_EN; 191 uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL; 192 uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; 193 uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY; 194 uint32_t DC_I2C_DDC1_HW_STATUS; 195 uint32_t DC_I2C_SW_DONE_USING_I2C_REG; 196 uint32_t DC_I2C_SW_USE_I2C_REG_REQ; 197 uint32_t DC_I2C_NO_QUEUED_SW_GO; 198 uint32_t DC_I2C_SW_PRIORITY; 199 uint32_t DC_I2C_SOFT_RESET; 200 uint32_t DC_I2C_SW_STATUS_RESET; 201 uint32_t DC_I2C_GO; 202 uint32_t DC_I2C_SEND_RESET; 203 uint32_t DC_I2C_TRANSACTION_COUNT; 204 uint32_t DC_I2C_DDC_SELECT; 205 uint32_t DC_I2C_DDC1_PRESCALE; 206 uint32_t DC_I2C_DDC1_THRESHOLD; 207 uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; 208 uint32_t DC_I2C_SW_STOPPED_ON_NACK; 209 uint32_t DC_I2C_SW_TIMEOUT; 210 uint32_t DC_I2C_SW_ABORTED; 211 uint32_t DC_I2C_SW_DONE; 212 uint32_t DC_I2C_SW_STATUS; 213 uint32_t DC_I2C_STOP_ON_NACK0; 214 uint32_t DC_I2C_START0; 215 uint32_t DC_I2C_RW0; 216 uint32_t DC_I2C_STOP0; 217 uint32_t DC_I2C_COUNT0; 218 uint32_t DC_I2C_DATA_RW; 219 uint32_t DC_I2C_DATA; 220 uint32_t DC_I2C_INDEX; 221 uint32_t DC_I2C_INDEX_WRITE; 222 uint32_t XTAL_REF_DIV; 223 uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH; 224 uint32_t DC_I2C_REG_RW_CNTL_STATUS; 225 }; 226 227 #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\ 228 I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\ 229 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh) 230 231 struct dce_i2c_registers { 232 uint32_t SETUP; 233 uint32_t SPEED; 234 uint32_t HW_STATUS; 235 uint32_t DC_I2C_ARBITRATION; 236 uint32_t DC_I2C_CONTROL; 237 uint32_t DC_I2C_SW_STATUS; 238 uint32_t DC_I2C_TRANSACTION0; 239 uint32_t DC_I2C_TRANSACTION1; 240 uint32_t DC_I2C_TRANSACTION2; 241 uint32_t DC_I2C_TRANSACTION3; 242 uint32_t DC_I2C_DATA; 243 uint32_t MICROSECOND_TIME_BASE_DIV; 244 }; 245 246 enum dce_i2c_transaction_address_space { 247 DCE_I2C_TRANSACTION_ADDRESS_SPACE_I2C = 1, 248 DCE_I2C_TRANSACTION_ADDRESS_SPACE_DPCD 249 }; 250 251 struct i2c_request_transaction_data { 252 enum dce_i2c_transaction_action action; 253 enum i2c_channel_operation_result status; 254 uint8_t address; 255 uint32_t length; 256 uint8_t *data; 257 }; 258 259 struct dce_i2c_hw { 260 struct ddc *ddc; 261 uint32_t engine_keep_power_up_count; 262 uint32_t transaction_count; 263 uint32_t buffer_used_bytes; 264 uint32_t buffer_used_write; 265 uint32_t reference_frequency; 266 uint32_t default_speed; 267 uint32_t engine_id; 268 uint32_t setup_limit; 269 uint32_t send_reset_length; 270 uint32_t buffer_size; 271 struct dc_context *ctx; 272 273 const struct dce_i2c_registers *regs; 274 const struct dce_i2c_shift *shifts; 275 const struct dce_i2c_mask *masks; 276 }; 277 278 void dce_i2c_hw_construct( 279 struct dce_i2c_hw *dce_i2c_hw, 280 struct dc_context *ctx, 281 uint32_t engine_id, 282 const struct dce_i2c_registers *regs, 283 const struct dce_i2c_shift *shifts, 284 const struct dce_i2c_mask *masks); 285 286 void dce100_i2c_hw_construct( 287 struct dce_i2c_hw *dce_i2c_hw, 288 struct dc_context *ctx, 289 uint32_t engine_id, 290 const struct dce_i2c_registers *regs, 291 const struct dce_i2c_shift *shifts, 292 const struct dce_i2c_mask *masks); 293 294 void dce112_i2c_hw_construct( 295 struct dce_i2c_hw *dce_i2c_hw, 296 struct dc_context *ctx, 297 uint32_t engine_id, 298 const struct dce_i2c_registers *regs, 299 const struct dce_i2c_shift *shifts, 300 const struct dce_i2c_mask *masks); 301 302 void dcn1_i2c_hw_construct( 303 struct dce_i2c_hw *dce_i2c_hw, 304 struct dc_context *ctx, 305 uint32_t engine_id, 306 const struct dce_i2c_registers *regs, 307 const struct dce_i2c_shift *shifts, 308 const struct dce_i2c_mask *masks); 309 310 void dcn2_i2c_hw_construct( 311 struct dce_i2c_hw *dce_i2c_hw, 312 struct dc_context *ctx, 313 uint32_t engine_id, 314 const struct dce_i2c_registers *regs, 315 const struct dce_i2c_shift *shifts, 316 const struct dce_i2c_mask *masks); 317 318 bool dce_i2c_submit_command_hw( 319 struct resource_pool *pool, 320 struct ddc *ddc, 321 struct i2c_command *cmd, 322 struct dce_i2c_hw *dce_i2c_hw); 323 324 struct dce_i2c_hw *acquire_i2c_hw_engine( 325 struct resource_pool *pool, 326 struct ddc *ddc); 327 328 #endif 329
Indexes created Sun Sep 21 20:09:37 GMT 2025