1 /* $NetBSD: dce110_timing_generator.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_TIMING_GENERATOR_DCE110_H__ 29 #define __DC_TIMING_GENERATOR_DCE110_H__ 30 31 #include "timing_generator.h" 32 #include "../include/grph_object_id.h" 33 34 /* GSL Sync related values */ 35 36 /* In VSync mode, after 4 units of time, master pipe will generate 37 * flip_ready signal */ 38 #define VFLIP_READY_DELAY 4 39 /* In HSync mode, after 2 units of time, master pipe will generate 40 * flip_ready signal */ 41 #define HFLIP_READY_DELAY 2 42 /* 6 lines delay between forcing flip and checking all pipes ready */ 43 #define HFLIP_CHECK_DELAY 6 44 /* 3 lines before end of frame */ 45 #define FLIP_READY_BACK_LOOKUP 3 46 47 /* Trigger Source Select - ASIC-defendant, actual values for the 48 * register programming */ 49 enum trigger_source_select { 50 TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0, 51 TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1, 52 TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2, 53 TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3, 54 TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4, 55 TRIGGER_SOURCE_SELECT_GENERICF = 5, 56 TRIGGER_SOURCE_SELECT_GENERICE = 6, 57 TRIGGER_SOURCE_SELECT_VSYNCA = 7, 58 TRIGGER_SOURCE_SELECT_HSYNCA = 8, 59 TRIGGER_SOURCE_SELECT_VSYNCB = 9, 60 TRIGGER_SOURCE_SELECT_HSYNCB = 10, 61 TRIGGER_SOURCE_SELECT_HPD1 = 11, 62 TRIGGER_SOURCE_SELECT_HPD2 = 12, 63 TRIGGER_SOURCE_SELECT_GENERICD = 13, 64 TRIGGER_SOURCE_SELECT_GENERICC = 14, 65 TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15, 66 TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16, 67 TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17, 68 TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18, 69 TRIGGER_SOURCE_SELECT_BLONY = 19, 70 TRIGGER_SOURCE_SELECT_GENERICA = 20, 71 TRIGGER_SOURCE_SELECT_GENERICB = 21, 72 TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22, 73 TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23 74 }; 75 76 /* Trigger Source Select - ASIC-dependant, actual values for the 77 * register programming */ 78 enum trigger_polarity_select { 79 TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0, 80 TRIGGER_POLARITY_SELECT_CRTC = 1, 81 TRIGGER_POLARITY_SELECT_GENERICA = 2, 82 TRIGGER_POLARITY_SELECT_GENERICB = 3, 83 TRIGGER_POLARITY_SELECT_HSYNCA = 4, 84 TRIGGER_POLARITY_SELECT_HSYNCB = 5, 85 TRIGGER_POLARITY_SELECT_VIDEO_CAPTURE = 6, 86 TRIGGER_POLARITY_SELECT_GENERICC = 7 87 }; 88 89 90 struct dce110_timing_generator_offsets { 91 int32_t crtc; 92 int32_t dcp; 93 94 /* DCE80 use only */ 95 int32_t dmif; 96 }; 97 98 struct dce110_timing_generator { 99 struct timing_generator base; 100 struct dce110_timing_generator_offsets offsets; 101 struct dce110_timing_generator_offsets derived_offsets; 102 103 enum controller_id controller_id; 104 105 uint32_t max_h_total; 106 uint32_t max_v_total; 107 108 uint32_t min_h_blank; 109 uint32_t min_h_front_porch; 110 uint32_t min_h_back_porch; 111 112 /* DCE 12 */ 113 uint32_t min_h_sync_width; 114 uint32_t min_v_sync_width; 115 uint32_t min_v_blank; 116 117 }; 118 119 #define DCE110TG_FROM_TG(tg)\ 120 container_of(tg, struct dce110_timing_generator, base) 121 122 void dce110_timing_generator_construct( 123 struct dce110_timing_generator *tg, 124 struct dc_context *ctx, 125 uint32_t instance, 126 const struct dce110_timing_generator_offsets *offsets); 127 128 /* determine if given timing can be supported by TG */ 129 bool dce110_timing_generator_validate_timing( 130 struct timing_generator *tg, 131 const struct dc_crtc_timing *timing, 132 enum signal_type signal); 133 134 /******** HW programming ************/ 135 136 /* Program timing generator with given timing */ 137 bool dce110_timing_generator_program_timing_generator( 138 struct timing_generator *tg, 139 const struct dc_crtc_timing *dc_crtc_timing); 140 141 /* Disable/Enable Timing Generator */ 142 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg); 143 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg); 144 145 void dce110_timing_generator_set_early_control( 146 struct timing_generator *tg, 147 uint32_t early_cntl); 148 149 /**************** TG current status ******************/ 150 151 /* return the current frame counter. Used by Linux kernel DRM */ 152 uint32_t dce110_timing_generator_get_vblank_counter( 153 struct timing_generator *tg); 154 155 void dce110_timing_generator_get_position( 156 struct timing_generator *tg, 157 struct crtc_position *position); 158 159 /* return true if TG counter is moving. false if TG is stopped */ 160 bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg); 161 162 /* wait until TG is in beginning of vertical blank region */ 163 void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg); 164 165 /* wait until TG is in beginning of active region */ 166 void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg); 167 168 /*********** Timing Generator Synchronization routines ****/ 169 170 /* Setups Global Swap Lock group, TimingServer or TimingClient*/ 171 void dce110_timing_generator_setup_global_swap_lock( 172 struct timing_generator *tg, 173 const struct dcp_gsl_params *gsl_params); 174 175 /* Clear all the register writes done by setup_global_swap_lock */ 176 void dce110_timing_generator_tear_down_global_swap_lock( 177 struct timing_generator *tg); 178 179 /* Reset crtc position on master VSync */ 180 void dce110_timing_generator_enable_crtc_reset( 181 struct timing_generator *tg, 182 int source, 183 struct crtc_trigger_info *crtc_tp); 184 185 /* Reset slave controllers on master VSync */ 186 void dce110_timing_generator_enable_reset_trigger( 187 struct timing_generator *tg, 188 int source); 189 190 /* disabling trigger-reset */ 191 void dce110_timing_generator_disable_reset_trigger( 192 struct timing_generator *tg); 193 194 /* Checks whether CRTC triggered reset occurred */ 195 bool dce110_timing_generator_did_triggered_reset_occur( 196 struct timing_generator *tg); 197 198 /******** Stuff to move to other virtual HW objects *****************/ 199 /* Move to enable accelerated mode */ 200 void dce110_timing_generator_disable_vga(struct timing_generator *tg); 201 /* TODO: Should we move it to transform */ 202 /* Fully program CRTC timing in timing generator */ 203 void dce110_timing_generator_program_blanking( 204 struct timing_generator *tg, 205 const struct dc_crtc_timing *timing); 206 207 /* TODO: Should we move it to opp? */ 208 /* Combine with below and move YUV/RGB color conversion to SW layer */ 209 void dce110_timing_generator_program_blank_color( 210 struct timing_generator *tg, 211 const struct tg_color *black_color); 212 /* Combine with above and move YUV/RGB color conversion to SW layer */ 213 void dce110_timing_generator_set_overscan_color_black( 214 struct timing_generator *tg, 215 const struct tg_color *color); 216 void dce110_timing_generator_color_space_to_black_color( 217 enum dc_color_space colorspace, 218 struct tg_color *black_color); 219 /*************** End-of-move ********************/ 220 221 /* Not called yet */ 222 void dce110_timing_generator_set_test_pattern( 223 struct timing_generator *tg, 224 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 225 * because this is not DP-specific (which is probably somewhere in DP 226 * encoder) */ 227 enum controller_dp_test_pattern test_pattern, 228 enum dc_color_depth color_depth); 229 230 void dce110_timing_generator_set_drr( 231 struct timing_generator *tg, 232 const struct drr_params *params); 233 234 void dce110_timing_generator_set_static_screen_control( 235 struct timing_generator *tg, 236 uint32_t event_triggers, 237 uint32_t num_frames); 238 239 void dce110_timing_generator_get_crtc_scanoutpos( 240 struct timing_generator *tg, 241 uint32_t *v_blank_start, 242 uint32_t *v_blank_end, 243 uint32_t *h_position, 244 uint32_t *v_position); 245 246 void dce110_timing_generator_enable_advanced_request( 247 struct timing_generator *tg, 248 bool enable, 249 const struct dc_crtc_timing *timing); 250 251 void dce110_timing_generator_set_lock_master(struct timing_generator *tg, 252 bool lock); 253 254 void dce110_tg_program_blank_color(struct timing_generator *tg, 255 const struct tg_color *black_color); 256 257 void dce110_tg_set_overscan_color(struct timing_generator *tg, 258 const struct tg_color *overscan_color); 259 260 void dce110_tg_program_timing(struct timing_generator *tg, 261 const struct dc_crtc_timing *timing, 262 int vready_offset, 263 int vstartup_start, 264 int vupdate_offset, 265 int vupdate_width, 266 const enum signal_type signal, 267 bool use_vbios); 268 269 bool dce110_tg_is_blanked(struct timing_generator *tg); 270 271 void dce110_tg_set_blank(struct timing_generator *tg, 272 bool enable_blanking); 273 274 bool dce110_tg_validate_timing(struct timing_generator *tg, 275 const struct dc_crtc_timing *timing); 276 277 void dce110_tg_wait_for_state(struct timing_generator *tg, 278 enum crtc_state state); 279 280 void dce110_tg_set_colors(struct timing_generator *tg, 281 const struct tg_color *blank_color, 282 const struct tg_color *overscan_color); 283 284 bool dce110_arm_vert_intr( 285 struct timing_generator *tg, uint8_t width); 286 287 bool dce110_configure_crc(struct timing_generator *tg, 288 const struct crc_params *params); 289 290 bool dce110_get_crc(struct timing_generator *tg, 291 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 292 293 #endif /* __DC_TIMING_GENERATOR_DCE110_H__ */ 294
Indexes created Mon Sep 22 13:09:51 GMT 2025