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      1 /*	$NetBSD: nouveau_nvkm_engine_sec2_tu102.c,v 1.2 2021/12/18 23:45:37 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Red Hat Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 #include <sys/cdefs.h>
     25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_sec2_tu102.c,v 1.2 2021/12/18 23:45:37 riastradh Exp $");
     26 
     27 #include "priv.h"
     28 #include <subdev/acr.h>
     29 
     30 static const struct nvkm_falcon_func
     31 tu102_sec2_flcn = {
     32 	.debug = 0x408,
     33 	.fbif = 0x600,
     34 	.load_imem = nvkm_falcon_v1_load_imem,
     35 	.load_dmem = nvkm_falcon_v1_load_dmem,
     36 	.read_dmem = nvkm_falcon_v1_read_dmem,
     37 	.emem_addr = 0x01000000,
     38 	.bind_context = gp102_sec2_flcn_bind_context,
     39 	.wait_for_halt = nvkm_falcon_v1_wait_for_halt,
     40 	.clear_interrupt = nvkm_falcon_v1_clear_interrupt,
     41 	.set_start_addr = nvkm_falcon_v1_set_start_addr,
     42 	.start = nvkm_falcon_v1_start,
     43 	.enable = nvkm_falcon_v1_enable,
     44 	.disable = nvkm_falcon_v1_disable,
     45 	.cmdq = { 0xc00, 0xc04, 8 },
     46 	.msgq = { 0xc80, 0xc84, 8 },
     47 };
     48 
     49 static const struct nvkm_sec2_func
     50 tu102_sec2 = {
     51 	.flcn = &tu102_sec2_flcn,
     52 	.unit_acr = 0x07,
     53 	.intr = gp102_sec2_intr,
     54 	.initmsg = gp102_sec2_initmsg,
     55 };
     56 
     57 static int
     58 tu102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
     59 		const struct nvkm_sec2_fwif *fwif)
     60 {
     61 	return 0;
     62 }
     63 
     64 static const struct nvkm_sec2_fwif
     65 tu102_sec2_fwif[] = {
     66 	{  0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
     67 	{ -1, tu102_sec2_nofw, &tu102_sec2 }
     68 };
     69 
     70 int
     71 tu102_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2)
     72 {
     73 	/* TOP info wasn't updated on Turing to reflect the PRI
     74 	 * address change for some reason.  We override it here.
     75 	 */
     76 	return nvkm_sec2_new_(tu102_sec2_fwif, device, index, 0x840000, psec2);
     77 }
     78