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      1 /*
      2  * Copyright (C) 2015 Jens Kuske <jenskuske (at) gmail.com>
      3  *
      4  * This file is dual-licensed: you can use it either under the terms
      5  * of the GPL or the X11 license, at your option. Note that this dual
      6  * licensing only applies to this file, and not this project as a
      7  * whole.
      8  *
      9  *  a) This file is free software; you can redistribute it and/or
     10  *     modify it under the terms of the GNU General Public License as
     11  *     published by the Free Software Foundation; either version 2 of the
     12  *     License, or (at your option) any later version.
     13  *
     14  *     This file is distributed in the hope that it will be useful,
     15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17  *     GNU General Public License for more details.
     18  *
     19  * Or, alternatively,
     20  *
     21  *  b) Permission is hereby granted, free of charge, to any person
     22  *     obtaining a copy of this software and associated documentation
     23  *     files (the "Software"), to deal in the Software without
     24  *     restriction, including without limitation the rights to use,
     25  *     copy, modify, merge, publish, distribute, sublicense, and/or
     26  *     sell copies of the Software, and to permit persons to whom the
     27  *     Software is furnished to do so, subject to the following
     28  *     conditions:
     29  *
     30  *     The above copyright notice and this permission notice shall be
     31  *     included in all copies or substantial portions of the Software.
     32  *
     33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     40  *     OTHER DEALINGS IN THE SOFTWARE.
     41  */
     42 
     43 #include <dt-bindings/clock/sun8i-de2.h>
     44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
     45 #include <dt-bindings/clock/sun8i-r-ccu.h>
     46 #include <dt-bindings/interrupt-controller/arm-gic.h>
     47 #include <dt-bindings/reset/sun8i-de2.h>
     48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
     49 #include <dt-bindings/reset/sun8i-r-ccu.h>
     50 
     51 / {
     52 	interrupt-parent = <&gic>;
     53 	#address-cells = <1>;
     54 	#size-cells = <1>;
     55 
     56 	chosen {
     57 		#address-cells = <1>;
     58 		#size-cells = <1>;
     59 		ranges;
     60 
     61 		framebuffer-hdmi {
     62 			compatible = "allwinner,simple-framebuffer",
     63 				     "simple-framebuffer";
     64 			allwinner,pipeline = "mixer0-lcd0-hdmi";
     65 			clocks = <&display_clocks CLK_MIXER0>,
     66 				 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
     67 			status = "disabled";
     68 		};
     69 
     70 		framebuffer-tve {
     71 			compatible = "allwinner,simple-framebuffer",
     72 				     "simple-framebuffer";
     73 			allwinner,pipeline = "mixer1-lcd1-tve";
     74 			clocks = <&display_clocks CLK_MIXER1>,
     75 				 <&ccu CLK_TVE>;
     76 			status = "disabled";
     77 		};
     78 	};
     79 
     80 	clocks {
     81 		#address-cells = <1>;
     82 		#size-cells = <1>;
     83 		ranges;
     84 
     85 		osc24M: osc24M_clk {
     86 			#clock-cells = <0>;
     87 			compatible = "fixed-clock";
     88 			clock-frequency = <24000000>;
     89 			clock-accuracy = <50000>;
     90 			clock-output-names = "osc24M";
     91 		};
     92 
     93 		osc32k: osc32k_clk {
     94 			#clock-cells = <0>;
     95 			compatible = "fixed-clock";
     96 			clock-frequency = <32768>;
     97 			clock-accuracy = <50000>;
     98 			clock-output-names = "ext_osc32k";
     99 		};
    100 	};
    101 
    102 	de: display-engine {
    103 		compatible = "allwinner,sun8i-h3-display-engine";
    104 		allwinner,pipelines = <&mixer0>;
    105 		status = "disabled";
    106 	};
    107 
    108 	soc {
    109 		compatible = "simple-bus";
    110 		#address-cells = <1>;
    111 		#size-cells = <1>;
    112 		dma-ranges;
    113 		ranges;
    114 
    115 		display_clocks: clock@1000000 {
    116 			/* compatible is in per SoC .dtsi file */
    117 			reg = <0x01000000 0x10000>;
    118 			clocks = <&ccu CLK_BUS_DE>,
    119 				 <&ccu CLK_DE>;
    120 			clock-names = "bus",
    121 				      "mod";
    122 			resets = <&ccu RST_BUS_DE>;
    123 			#clock-cells = <1>;
    124 			#reset-cells = <1>;
    125 		};
    126 
    127 		mixer0: mixer@1100000 {
    128 			compatible = "allwinner,sun8i-h3-de2-mixer-0";
    129 			reg = <0x01100000 0x100000>;
    130 			clocks = <&display_clocks CLK_BUS_MIXER0>,
    131 				 <&display_clocks CLK_MIXER0>;
    132 			clock-names = "bus",
    133 				      "mod";
    134 			resets = <&display_clocks RST_MIXER0>;
    135 
    136 			ports {
    137 				#address-cells = <1>;
    138 				#size-cells = <0>;
    139 
    140 				mixer0_out: port@1 {
    141 					reg = <1>;
    142 
    143 					mixer0_out_tcon0: endpoint {
    144 						remote-endpoint = <&tcon0_in_mixer0>;
    145 					};
    146 				};
    147 			};
    148 		};
    149 
    150 		dma: dma-controller@1c02000 {
    151 			compatible = "allwinner,sun8i-h3-dma";
    152 			reg = <0x01c02000 0x1000>;
    153 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
    154 			clocks = <&ccu CLK_BUS_DMA>;
    155 			resets = <&ccu RST_BUS_DMA>;
    156 			#dma-cells = <1>;
    157 		};
    158 
    159 		tcon0: lcd-controller@1c0c000 {
    160 			compatible = "allwinner,sun8i-h3-tcon-tv",
    161 				     "allwinner,sun8i-a83t-tcon-tv";
    162 			reg = <0x01c0c000 0x1000>;
    163 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
    164 			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
    165 			clock-names = "ahb", "tcon-ch1";
    166 			resets = <&ccu RST_BUS_TCON0>;
    167 			reset-names = "lcd";
    168 
    169 			ports {
    170 				#address-cells = <1>;
    171 				#size-cells = <0>;
    172 
    173 				tcon0_in: port@0 {
    174 					reg = <0>;
    175 
    176 					tcon0_in_mixer0: endpoint {
    177 						remote-endpoint = <&mixer0_out_tcon0>;
    178 					};
    179 				};
    180 
    181 				tcon0_out: port@1 {
    182 					#address-cells = <1>;
    183 					#size-cells = <0>;
    184 					reg = <1>;
    185 
    186 					tcon0_out_hdmi: endpoint@1 {
    187 						reg = <1>;
    188 						remote-endpoint = <&hdmi_in_tcon0>;
    189 					};
    190 				};
    191 			};
    192 		};
    193 
    194 		mmc0: mmc@1c0f000 {
    195 			/* compatible and clocks are in per SoC .dtsi file */
    196 			reg = <0x01c0f000 0x1000>;
    197 			pinctrl-names = "default";
    198 			pinctrl-0 = <&mmc0_pins>;
    199 			resets = <&ccu RST_BUS_MMC0>;
    200 			reset-names = "ahb";
    201 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
    202 			status = "disabled";
    203 			#address-cells = <1>;
    204 			#size-cells = <0>;
    205 		};
    206 
    207 		mmc1: mmc@1c10000 {
    208 			/* compatible and clocks are in per SoC .dtsi file */
    209 			reg = <0x01c10000 0x1000>;
    210 			pinctrl-names = "default";
    211 			pinctrl-0 = <&mmc1_pins>;
    212 			resets = <&ccu RST_BUS_MMC1>;
    213 			reset-names = "ahb";
    214 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
    215 			status = "disabled";
    216 			#address-cells = <1>;
    217 			#size-cells = <0>;
    218 		};
    219 
    220 		mmc2: mmc@1c11000 {
    221 			/* compatible and clocks are in per SoC .dtsi file */
    222 			reg = <0x01c11000 0x1000>;
    223 			resets = <&ccu RST_BUS_MMC2>;
    224 			reset-names = "ahb";
    225 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
    226 			status = "disabled";
    227 			#address-cells = <1>;
    228 			#size-cells = <0>;
    229 		};
    230 
    231 		sid: eeprom@1c14000 {
    232 			/* compatible is in per SoC .dtsi file */
    233 			reg = <0x1c14000 0x400>;
    234 			#address-cells = <1>;
    235 			#size-cells = <1>;
    236 
    237 			ths_calibration: thermal-sensor-calibration@34 {
    238 				reg = <0x34 4>;
    239 			};
    240 		};
    241 
    242 		msgbox: mailbox@1c17000 {
    243 			compatible = "allwinner,sun8i-h3-msgbox",
    244 				     "allwinner,sun6i-a31-msgbox";
    245 			reg = <0x01c17000 0x1000>;
    246 			clocks = <&ccu CLK_BUS_MSGBOX>;
    247 			resets = <&ccu RST_BUS_MSGBOX>;
    248 			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
    249 			#mbox-cells = <1>;
    250 		};
    251 
    252 		usb_otg: usb@1c19000 {
    253 			compatible = "allwinner,sun8i-h3-musb";
    254 			reg = <0x01c19000 0x400>;
    255 			clocks = <&ccu CLK_BUS_OTG>;
    256 			resets = <&ccu RST_BUS_OTG>;
    257 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
    258 			interrupt-names = "mc";
    259 			phys = <&usbphy 0>;
    260 			phy-names = "usb";
    261 			extcon = <&usbphy 0>;
    262 			dr_mode = "otg";
    263 			status = "disabled";
    264 		};
    265 
    266 		usbphy: phy@1c19400 {
    267 			compatible = "allwinner,sun8i-h3-usb-phy";
    268 			reg = <0x01c19400 0x2c>,
    269 			      <0x01c1a800 0x4>,
    270 			      <0x01c1b800 0x4>,
    271 			      <0x01c1c800 0x4>,
    272 			      <0x01c1d800 0x4>;
    273 			reg-names = "phy_ctrl",
    274 				    "pmu0",
    275 				    "pmu1",
    276 				    "pmu2",
    277 				    "pmu3";
    278 			clocks = <&ccu CLK_USB_PHY0>,
    279 				 <&ccu CLK_USB_PHY1>,
    280 				 <&ccu CLK_USB_PHY2>,
    281 				 <&ccu CLK_USB_PHY3>;
    282 			clock-names = "usb0_phy",
    283 				      "usb1_phy",
    284 				      "usb2_phy",
    285 				      "usb3_phy";
    286 			resets = <&ccu RST_USB_PHY0>,
    287 				 <&ccu RST_USB_PHY1>,
    288 				 <&ccu RST_USB_PHY2>,
    289 				 <&ccu RST_USB_PHY3>;
    290 			reset-names = "usb0_reset",
    291 				      "usb1_reset",
    292 				      "usb2_reset",
    293 				      "usb3_reset";
    294 			status = "disabled";
    295 			#phy-cells = <1>;
    296 		};
    297 
    298 		ehci0: usb@1c1a000 {
    299 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
    300 			reg = <0x01c1a000 0x100>;
    301 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
    302 			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
    303 			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
    304 			status = "disabled";
    305 		};
    306 
    307 		ohci0: usb@1c1a400 {
    308 			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
    309 			reg = <0x01c1a400 0x100>;
    310 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
    311 			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
    312 				 <&ccu CLK_USB_OHCI0>;
    313 			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
    314 			status = "disabled";
    315 		};
    316 
    317 		ehci1: usb@1c1b000 {
    318 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
    319 			reg = <0x01c1b000 0x100>;
    320 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
    321 			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
    322 			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
    323 			phys = <&usbphy 1>;
    324 			phy-names = "usb";
    325 			status = "disabled";
    326 		};
    327 
    328 		ohci1: usb@1c1b400 {
    329 			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
    330 			reg = <0x01c1b400 0x100>;
    331 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
    332 			clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
    333 				 <&ccu CLK_USB_OHCI1>;
    334 			resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
    335 			phys = <&usbphy 1>;
    336 			phy-names = "usb";
    337 			status = "disabled";
    338 		};
    339 
    340 		ehci2: usb@1c1c000 {
    341 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
    342 			reg = <0x01c1c000 0x100>;
    343 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
    344 			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
    345 			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
    346 			phys = <&usbphy 2>;
    347 			phy-names = "usb";
    348 			status = "disabled";
    349 		};
    350 
    351 		ohci2: usb@1c1c400 {
    352 			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
    353 			reg = <0x01c1c400 0x100>;
    354 			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
    355 			clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
    356 				 <&ccu CLK_USB_OHCI2>;
    357 			resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
    358 			phys = <&usbphy 2>;
    359 			phy-names = "usb";
    360 			status = "disabled";
    361 		};
    362 
    363 		ehci3: usb@1c1d000 {
    364 			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
    365 			reg = <0x01c1d000 0x100>;
    366 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
    367 			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
    368 			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
    369 			phys = <&usbphy 3>;
    370 			phy-names = "usb";
    371 			status = "disabled";
    372 		};
    373 
    374 		ohci3: usb@1c1d400 {
    375 			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
    376 			reg = <0x01c1d400 0x100>;
    377 			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
    378 			clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
    379 				 <&ccu CLK_USB_OHCI3>;
    380 			resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
    381 			phys = <&usbphy 3>;
    382 			phy-names = "usb";
    383 			status = "disabled";
    384 		};
    385 
    386 		ccu: clock@1c20000 {
    387 			/* compatible is in per SoC .dtsi file */
    388 			reg = <0x01c20000 0x400>;
    389 			clocks = <&osc24M>, <&rtc 0>;
    390 			clock-names = "hosc", "losc";
    391 			#clock-cells = <1>;
    392 			#reset-cells = <1>;
    393 		};
    394 
    395 		pio: pinctrl@1c20800 {
    396 			/* compatible is in per SoC .dtsi file */
    397 			reg = <0x01c20800 0x400>;
    398 			interrupt-parent = <&r_intc>;
    399 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
    400 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
    401 			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
    402 			clock-names = "apb", "hosc", "losc";
    403 			gpio-controller;
    404 			#gpio-cells = <3>;
    405 			interrupt-controller;
    406 			#interrupt-cells = <3>;
    407 
    408 			csi_pins: csi-pins {
    409 				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
    410 				       "PE6", "PE7", "PE8", "PE9", "PE10",
    411 				       "PE11";
    412 				function = "csi";
    413 			};
    414 
    415 			emac_rgmii_pins: emac-rgmii-pins {
    416 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
    417 				       "PD5", "PD7", "PD8", "PD9", "PD10",
    418 				       "PD12", "PD13", "PD15", "PD16", "PD17";
    419 				function = "emac";
    420 				drive-strength = <40>;
    421 			};
    422 
    423 			i2c0_pins: i2c0-pins {
    424 				pins = "PA11", "PA12";
    425 				function = "i2c0";
    426 			};
    427 
    428 			i2c1_pins: i2c1-pins {
    429 				pins = "PA18", "PA19";
    430 				function = "i2c1";
    431 			};
    432 
    433 			i2c2_pins: i2c2-pins {
    434 				pins = "PE12", "PE13";
    435 				function = "i2c2";
    436 			};
    437 
    438 			mmc0_pins: mmc0-pins {
    439 				pins = "PF0", "PF1", "PF2", "PF3",
    440 				       "PF4", "PF5";
    441 				function = "mmc0";
    442 				drive-strength = <30>;
    443 				bias-pull-up;
    444 			};
    445 
    446 			mmc1_pins: mmc1-pins {
    447 				pins = "PG0", "PG1", "PG2", "PG3",
    448 				       "PG4", "PG5";
    449 				function = "mmc1";
    450 				drive-strength = <30>;
    451 				bias-pull-up;
    452 			};
    453 
    454 			mmc2_8bit_pins: mmc2-8bit-pins {
    455 				pins = "PC5", "PC6", "PC8",
    456 				       "PC9", "PC10", "PC11",
    457 				       "PC12", "PC13", "PC14",
    458 				       "PC15", "PC16";
    459 				function = "mmc2";
    460 				drive-strength = <30>;
    461 				bias-pull-up;
    462 			};
    463 
    464 			spdif_tx_pin: spdif-tx-pin {
    465 				pins = "PA17";
    466 				function = "spdif";
    467 			};
    468 
    469 			spi0_pins: spi0-pins {
    470 				pins = "PC0", "PC1", "PC2", "PC3";
    471 				function = "spi0";
    472 			};
    473 
    474 			spi1_pins: spi1-pins {
    475 				pins = "PA15", "PA16", "PA14", "PA13";
    476 				function = "spi1";
    477 			};
    478 
    479 			uart0_pa_pins: uart0-pa-pins {
    480 				pins = "PA4", "PA5";
    481 				function = "uart0";
    482 			};
    483 
    484 			uart1_pins: uart1-pins {
    485 				pins = "PG6", "PG7";
    486 				function = "uart1";
    487 			};
    488 
    489 			uart1_rts_cts_pins: uart1-rts-cts-pins {
    490 				pins = "PG8", "PG9";
    491 				function = "uart1";
    492 			};
    493 
    494 			uart2_pins: uart2-pins {
    495 				pins = "PA0", "PA1";
    496 				function = "uart2";
    497 			};
    498 
    499 			uart2_rts_cts_pins: uart2-rts-cts-pins {
    500 				pins = "PA2", "PA3";
    501 				function = "uart2";
    502 			};
    503 
    504 			uart3_pins: uart3-pins {
    505 				pins = "PA13", "PA14";
    506 				function = "uart3";
    507 			};
    508 
    509 			uart3_rts_cts_pins: uart3-rts-cts-pins {
    510 				pins = "PA15", "PA16";
    511 				function = "uart3";
    512 			};
    513 		};
    514 
    515 		timer@1c20c00 {
    516 			compatible = "allwinner,sun8i-a23-timer";
    517 			reg = <0x01c20c00 0xa0>;
    518 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
    519 				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
    520 			clocks = <&osc24M>;
    521 		};
    522 
    523 		emac: ethernet@1c30000 {
    524 			compatible = "allwinner,sun8i-h3-emac";
    525 			syscon = <&syscon>;
    526 			reg = <0x01c30000 0x10000>;
    527 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
    528 			interrupt-names = "macirq";
    529 			resets = <&ccu RST_BUS_EMAC>;
    530 			reset-names = "stmmaceth";
    531 			clocks = <&ccu CLK_BUS_EMAC>;
    532 			clock-names = "stmmaceth";
    533 			status = "disabled";
    534 
    535 			mdio: mdio {
    536 				#address-cells = <1>;
    537 				#size-cells = <0>;
    538 				compatible = "snps,dwmac-mdio";
    539 			};
    540 
    541 			mdio-mux {
    542 				compatible = "allwinner,sun8i-h3-mdio-mux";
    543 				#address-cells = <1>;
    544 				#size-cells = <0>;
    545 
    546 				mdio-parent-bus = <&mdio>;
    547 				/* Only one MDIO is usable at the time */
    548 				internal_mdio: mdio@1 {
    549 					compatible = "allwinner,sun8i-h3-mdio-internal";
    550 					reg = <1>;
    551 					#address-cells = <1>;
    552 					#size-cells = <0>;
    553 
    554 					int_mii_phy: ethernet-phy@1 {
    555 						compatible = "ethernet-phy-ieee802.3-c22";
    556 						reg = <1>;
    557 						clocks = <&ccu CLK_BUS_EPHY>;
    558 						resets = <&ccu RST_BUS_EPHY>;
    559 					};
    560 				};
    561 
    562 				external_mdio: mdio@2 {
    563 					reg = <2>;
    564 					#address-cells = <1>;
    565 					#size-cells = <0>;
    566 				};
    567 			};
    568 		};
    569 
    570 		mbus: dram-controller@1c62000 {
    571 			compatible = "allwinner,sun8i-h3-mbus";
    572 			reg = <0x01c62000 0x1000>;
    573 			clocks = <&ccu CLK_MBUS>;
    574 			#address-cells = <1>;
    575 			#size-cells = <1>;
    576 			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
    577 			#interconnect-cells = <1>;
    578 		};
    579 
    580 		spi0: spi@1c68000 {
    581 			compatible = "allwinner,sun8i-h3-spi";
    582 			reg = <0x01c68000 0x1000>;
    583 			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
    584 			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
    585 			clock-names = "ahb", "mod";
    586 			dmas = <&dma 23>, <&dma 23>;
    587 			dma-names = "rx", "tx";
    588 			pinctrl-names = "default";
    589 			pinctrl-0 = <&spi0_pins>;
    590 			resets = <&ccu RST_BUS_SPI0>;
    591 			status = "disabled";
    592 			#address-cells = <1>;
    593 			#size-cells = <0>;
    594 		};
    595 
    596 		spi1: spi@1c69000 {
    597 			compatible = "allwinner,sun8i-h3-spi";
    598 			reg = <0x01c69000 0x1000>;
    599 			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
    600 			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
    601 			clock-names = "ahb", "mod";
    602 			dmas = <&dma 24>, <&dma 24>;
    603 			dma-names = "rx", "tx";
    604 			pinctrl-names = "default";
    605 			pinctrl-0 = <&spi1_pins>;
    606 			resets = <&ccu RST_BUS_SPI1>;
    607 			status = "disabled";
    608 			#address-cells = <1>;
    609 			#size-cells = <0>;
    610 		};
    611 
    612 		wdt0: watchdog@1c20ca0 {
    613 			compatible = "allwinner,sun6i-a31-wdt";
    614 			reg = <0x01c20ca0 0x20>;
    615 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
    616 			clocks = <&osc24M>;
    617 		};
    618 
    619 		spdif: spdif@1c21000 {
    620 			#sound-dai-cells = <0>;
    621 			compatible = "allwinner,sun8i-h3-spdif";
    622 			reg = <0x01c21000 0x400>;
    623 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
    624 			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
    625 			resets = <&ccu RST_BUS_SPDIF>;
    626 			clock-names = "apb", "spdif";
    627 			dmas = <&dma 2>;
    628 			dma-names = "tx";
    629 			status = "disabled";
    630 		};
    631 
    632 		pwm: pwm@1c21400 {
    633 			compatible = "allwinner,sun8i-h3-pwm";
    634 			reg = <0x01c21400 0x8>;
    635 			clocks = <&osc24M>;
    636 			#pwm-cells = <3>;
    637 			status = "disabled";
    638 		};
    639 
    640 		i2s0: i2s@1c22000 {
    641 			#sound-dai-cells = <0>;
    642 			compatible = "allwinner,sun8i-h3-i2s";
    643 			reg = <0x01c22000 0x400>;
    644 			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
    645 			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
    646 			clock-names = "apb", "mod";
    647 			dmas = <&dma 3>, <&dma 3>;
    648 			resets = <&ccu RST_BUS_I2S0>;
    649 			dma-names = "rx", "tx";
    650 			status = "disabled";
    651 		};
    652 
    653 		i2s1: i2s@1c22400 {
    654 			#sound-dai-cells = <0>;
    655 			compatible = "allwinner,sun8i-h3-i2s";
    656 			reg = <0x01c22400 0x400>;
    657 			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    658 			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
    659 			clock-names = "apb", "mod";
    660 			dmas = <&dma 4>, <&dma 4>;
    661 			resets = <&ccu RST_BUS_I2S1>;
    662 			dma-names = "rx", "tx";
    663 			status = "disabled";
    664 		};
    665 
    666 		i2s2: i2s@1c22800 {
    667 			#sound-dai-cells = <0>;
    668 			compatible = "allwinner,sun8i-h3-i2s";
    669 			reg = <0x01c22800 0x400>;
    670 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    671 			clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
    672 			clock-names = "apb", "mod";
    673 			dmas = <&dma 27>;
    674 			resets = <&ccu RST_BUS_I2S2>;
    675 			dma-names = "tx";
    676 			status = "disabled";
    677 		};
    678 
    679 		codec: codec@1c22c00 {
    680 			#sound-dai-cells = <0>;
    681 			compatible = "allwinner,sun8i-h3-codec";
    682 			reg = <0x01c22c00 0x400>;
    683 			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
    684 			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
    685 			clock-names = "apb", "codec";
    686 			resets = <&ccu RST_BUS_CODEC>;
    687 			dmas = <&dma 15>, <&dma 15>;
    688 			dma-names = "rx", "tx";
    689 			allwinner,codec-analog-controls = <&codec_analog>;
    690 			status = "disabled";
    691 		};
    692 
    693 		uart0: serial@1c28000 {
    694 			compatible = "snps,dw-apb-uart";
    695 			reg = <0x01c28000 0x400>;
    696 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
    697 			reg-shift = <2>;
    698 			reg-io-width = <4>;
    699 			clocks = <&ccu CLK_BUS_UART0>;
    700 			resets = <&ccu RST_BUS_UART0>;
    701 			dmas = <&dma 6>, <&dma 6>;
    702 			dma-names = "rx", "tx";
    703 			status = "disabled";
    704 		};
    705 
    706 		uart1: serial@1c28400 {
    707 			compatible = "snps,dw-apb-uart";
    708 			reg = <0x01c28400 0x400>;
    709 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
    710 			reg-shift = <2>;
    711 			reg-io-width = <4>;
    712 			clocks = <&ccu CLK_BUS_UART1>;
    713 			resets = <&ccu RST_BUS_UART1>;
    714 			dmas = <&dma 7>, <&dma 7>;
    715 			dma-names = "rx", "tx";
    716 			status = "disabled";
    717 		};
    718 
    719 		uart2: serial@1c28800 {
    720 			compatible = "snps,dw-apb-uart";
    721 			reg = <0x01c28800 0x400>;
    722 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
    723 			reg-shift = <2>;
    724 			reg-io-width = <4>;
    725 			clocks = <&ccu CLK_BUS_UART2>;
    726 			resets = <&ccu RST_BUS_UART2>;
    727 			dmas = <&dma 8>, <&dma 8>;
    728 			dma-names = "rx", "tx";
    729 			status = "disabled";
    730 		};
    731 
    732 		uart3: serial@1c28c00 {
    733 			compatible = "snps,dw-apb-uart";
    734 			reg = <0x01c28c00 0x400>;
    735 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
    736 			reg-shift = <2>;
    737 			reg-io-width = <4>;
    738 			clocks = <&ccu CLK_BUS_UART3>;
    739 			resets = <&ccu RST_BUS_UART3>;
    740 			dmas = <&dma 9>, <&dma 9>;
    741 			dma-names = "rx", "tx";
    742 			status = "disabled";
    743 		};
    744 
    745 		i2c0: i2c@1c2ac00 {
    746 			compatible = "allwinner,sun6i-a31-i2c";
    747 			reg = <0x01c2ac00 0x400>;
    748 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
    749 			clocks = <&ccu CLK_BUS_I2C0>;
    750 			resets = <&ccu RST_BUS_I2C0>;
    751 			pinctrl-names = "default";
    752 			pinctrl-0 = <&i2c0_pins>;
    753 			status = "disabled";
    754 			#address-cells = <1>;
    755 			#size-cells = <0>;
    756 		};
    757 
    758 		i2c1: i2c@1c2b000 {
    759 			compatible = "allwinner,sun6i-a31-i2c";
    760 			reg = <0x01c2b000 0x400>;
    761 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
    762 			clocks = <&ccu CLK_BUS_I2C1>;
    763 			resets = <&ccu RST_BUS_I2C1>;
    764 			pinctrl-names = "default";
    765 			pinctrl-0 = <&i2c1_pins>;
    766 			status = "disabled";
    767 			#address-cells = <1>;
    768 			#size-cells = <0>;
    769 		};
    770 
    771 		i2c2: i2c@1c2b400 {
    772 			compatible = "allwinner,sun6i-a31-i2c";
    773 			reg = <0x01c2b400 0x400>;
    774 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
    775 			clocks = <&ccu CLK_BUS_I2C2>;
    776 			resets = <&ccu RST_BUS_I2C2>;
    777 			pinctrl-names = "default";
    778 			pinctrl-0 = <&i2c2_pins>;
    779 			status = "disabled";
    780 			#address-cells = <1>;
    781 			#size-cells = <0>;
    782 		};
    783 
    784 		gic: interrupt-controller@1c81000 {
    785 			compatible = "arm,gic-400";
    786 			reg = <0x01c81000 0x1000>,
    787 			      <0x01c82000 0x2000>,
    788 			      <0x01c84000 0x2000>,
    789 			      <0x01c86000 0x2000>;
    790 			interrupt-controller;
    791 			#interrupt-cells = <3>;
    792 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
    793 		};
    794 
    795 		csi: camera@1cb0000 {
    796 			compatible = "allwinner,sun8i-h3-csi";
    797 			reg = <0x01cb0000 0x1000>;
    798 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
    799 			clocks = <&ccu CLK_BUS_CSI>,
    800 				 <&ccu CLK_CSI_SCLK>,
    801 				 <&ccu CLK_DRAM_CSI>;
    802 			clock-names = "bus", "mod", "ram";
    803 			resets = <&ccu RST_BUS_CSI>;
    804 			pinctrl-names = "default";
    805 			pinctrl-0 = <&csi_pins>;
    806 			status = "disabled";
    807 		};
    808 
    809 		hdmi: hdmi@1ee0000 {
    810 			compatible = "allwinner,sun8i-h3-dw-hdmi",
    811 				     "allwinner,sun8i-a83t-dw-hdmi";
    812 			reg = <0x01ee0000 0x10000>;
    813 			reg-io-width = <1>;
    814 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
    815 			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
    816 				 <&ccu CLK_HDMI>;
    817 			clock-names = "iahb", "isfr", "tmds";
    818 			resets = <&ccu RST_BUS_HDMI1>;
    819 			reset-names = "ctrl";
    820 			phys = <&hdmi_phy>;
    821 			phy-names = "phy";
    822 			status = "disabled";
    823 
    824 			ports {
    825 				#address-cells = <1>;
    826 				#size-cells = <0>;
    827 
    828 				hdmi_in: port@0 {
    829 					reg = <0>;
    830 
    831 					hdmi_in_tcon0: endpoint {
    832 						remote-endpoint = <&tcon0_out_hdmi>;
    833 					};
    834 				};
    835 
    836 				hdmi_out: port@1 {
    837 					reg = <1>;
    838 				};
    839 			};
    840 		};
    841 
    842 		hdmi_phy: hdmi-phy@1ef0000 {
    843 			compatible = "allwinner,sun8i-h3-hdmi-phy";
    844 			reg = <0x01ef0000 0x10000>;
    845 			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
    846 				 <&ccu CLK_PLL_VIDEO>;
    847 			clock-names = "bus", "mod", "pll-0";
    848 			resets = <&ccu RST_BUS_HDMI0>;
    849 			reset-names = "phy";
    850 			#phy-cells = <0>;
    851 		};
    852 
    853 		rtc: rtc@1f00000 {
    854 			/* compatible is in per SoC .dtsi file */
    855 			reg = <0x01f00000 0x400>;
    856 			interrupt-parent = <&r_intc>;
    857 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
    858 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
    859 			clock-output-names = "osc32k", "osc32k-out", "iosc";
    860 			clocks = <&osc32k>;
    861 			#clock-cells = <1>;
    862 		};
    863 
    864 		r_intc: interrupt-controller@1f00c00 {
    865 			compatible = "allwinner,sun8i-h3-r-intc",
    866 				     "allwinner,sun6i-a31-r-intc";
    867 			interrupt-controller;
    868 			#interrupt-cells = <3>;
    869 			reg = <0x01f00c00 0x400>;
    870 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    871 		};
    872 
    873 		r_ccu: clock@1f01400 {
    874 			compatible = "allwinner,sun8i-h3-r-ccu";
    875 			reg = <0x01f01400 0x100>;
    876 			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
    877 				 <&ccu CLK_PLL_PERIPH0>;
    878 			clock-names = "hosc", "losc", "iosc", "pll-periph";
    879 			#clock-cells = <1>;
    880 			#reset-cells = <1>;
    881 		};
    882 
    883 		codec_analog: codec-analog@1f015c0 {
    884 			compatible = "allwinner,sun8i-h3-codec-analog";
    885 			reg = <0x01f015c0 0x4>;
    886 		};
    887 
    888 		ir: ir@1f02000 {
    889 			compatible = "allwinner,sun6i-a31-ir";
    890 			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
    891 			clock-names = "apb", "ir";
    892 			resets = <&r_ccu RST_APB0_IR>;
    893 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
    894 			reg = <0x01f02000 0x400>;
    895 			status = "disabled";
    896 		};
    897 
    898 		r_i2c: i2c@1f02400 {
    899 			compatible = "allwinner,sun6i-a31-i2c";
    900 			reg = <0x01f02400 0x400>;
    901 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
    902 			pinctrl-names = "default";
    903 			pinctrl-0 = <&r_i2c_pins>;
    904 			clocks = <&r_ccu CLK_APB0_I2C>;
    905 			resets = <&r_ccu RST_APB0_I2C>;
    906 			status = "disabled";
    907 			#address-cells = <1>;
    908 			#size-cells = <0>;
    909 		};
    910 
    911 		r_pio: pinctrl@1f02c00 {
    912 			compatible = "allwinner,sun8i-h3-r-pinctrl";
    913 			reg = <0x01f02c00 0x400>;
    914 			interrupt-parent = <&r_intc>;
    915 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
    916 			clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
    917 			clock-names = "apb", "hosc", "losc";
    918 			gpio-controller;
    919 			#gpio-cells = <3>;
    920 			interrupt-controller;
    921 			#interrupt-cells = <3>;
    922 
    923 			r_ir_rx_pin: r-ir-rx-pin {
    924 				pins = "PL11";
    925 				function = "s_cir_rx";
    926 			};
    927 
    928 			r_i2c_pins: r-i2c-pins {
    929 				pins = "PL0", "PL1";
    930 				function = "s_i2c";
    931 			};
    932 
    933 			r_pwm_pin: r-pwm-pin {
    934 				pins = "PL10";
    935 				function = "s_pwm";
    936 			};
    937 		};
    938 
    939 		r_pwm: pwm@1f03800 {
    940 			compatible = "allwinner,sun8i-h3-pwm";
    941 			reg = <0x01f03800 0x8>;
    942 			pinctrl-names = "default";
    943 			pinctrl-0 = <&r_pwm_pin>;
    944 			clocks = <&osc24M>;
    945 			#pwm-cells = <3>;
    946 			status = "disabled";
    947 		};
    948 	};
    949 };
    950