1 /* $NetBSD: hdc9224.h,v 1.7 2017/05/22 17:17:25 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Ludd by Bertram Barth. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 30 struct hdc9224_DKCreg { 31 unsigned char dkc_reg; /* Disk Register Data Access Port (rw)*/ 32 unsigned char fill[3]; /* bytes are longword aligned */ 33 unsigned char dkc_cmd; /* Disk Controller Command Port (wo) */ 34 #define dkc_stat dkc_cmd /* Interrupt Status Port (ro) */ 35 }; 36 37 /* 38 * definition of some commands (constant bits only, incomplete!) 39 */ 40 #define DKC_CMD_RESET 0x00 /* terminate non-data-transfer cmds */ 41 #define DKC_CMD_DRDESELECT 0x01 /* done when no drive is in use */ 42 #define DKC_CMD_SETREGPTR 0x40 /* logically or-ed with reg-number */ 43 #define DKC_CMD_DRSELECT 0x20 44 #define DKC_CMD_DRSEL_HDD 0x24 /* select HDD, or-ed with unit-numb. */ 45 #define DKC_CMD_DRSEL_RX33 0x28 /* or-ed with unit-number of RX33 */ 46 #define DKC_CMD_DRSEL_RX50 0x2C /* or-ed with unit-number of RX50 */ 47 #define DKC_CMD_RESTORE 0x02 48 #define DKC_CMD_STEP 0x04 49 #define DKC_CMD_STEPIN_FDD 0x04 /* one step inward for floppy */ 50 #define DKC_CMD_STEPOUT_FDD 0x06 /* one step outward (toward cyl #0) */ 51 #define DKC_CMD_POLLDRIVE 0x10 52 #define DKC_CMD_SEEKREADID 0x50 53 #define DKC_CMD_FORMATTRACK 0x60 54 #define DKC_CMD_READTRACK 0x5A 55 #define DKC_CMD_READPHYSICAL 0x58 56 #define DKC_CMD_READLOGICAL 0x5C 57 #define DKC_CMD_READ_HDD 0x5D /* read-logical, bypass=0, xfer=1 */ 58 #define DKC_CMD_READ_RX33 0x5D /* ??? */ 59 #define DKC_CMD_WRITEPHYSICAL 0x80 60 #define DKC_CMD_WRITELOGICAL 0xC0 61 #define DKC_CMD_WRITE_HDD 0xA0 /* bypass=0, ddmark=0 */ 62 #define DKC_CMD_WRITE_RX33 0xA1 /* precompensation differs... */ 63 #define DKC_CMD_WRITE_RX50 0xA4 64 65 /* 66 * Definition of bits in the DKC_STAT register 67 */ 68 #define DKC_ST_INTPEND (1<<7) /* interrupt pending */ 69 #define DKC_ST_DMAREQ (1<<6) /* DMA request */ 70 #define DKC_ST_DONE (1<<5) /* command done */ 71 #define DKC_ST_TERMCOD (3<<3) /* termination code (see below) */ 72 #define DKC_ST_RDYCHNG (1<<2) /* ready change */ 73 #define DKC_ST_OVRUN (1<<1) /* overrun/underrun */ 74 #define DKC_ST_BADSECT (1<<0) /* bad sector */ 75 76 /* 77 * Definition of the termination codes 78 */ 79 #define DKC_TC_SUCCESS (0<<3) /* Successful completion */ 80 #define DKC_TC_RDIDERR (1<<3) /* Error in READ-ID sequence */ 81 #define DKC_TC_VRFYERR (2<<3) /* Error in VERIFY sequence */ 82 #define DKC_TC_DATAERR (3<<3) /* Error in DATA-TRANSFER seq. */ 83 84 /* 85 * Definitions of delays necessary for floppy-operation 86 */ 87 #define DKC_DELAY_MOTOR 500 /* allow 500 ms to reach speed */ 88 #define DKC_DELAY_SELECT 70 /* 70 ms for data-recovery-circuit */ 89 #define DKC_DELAY_POSITION 59 /* 59 ms for RX33, 100 ms for RX50 */ 90 #define DKC_DELAY_HEADSET 18 /* 18 ms when changing head-number */ 91 92 /* 93 * The HDC9224 has 11/15(?) internal registers which are accessible via 94 * the Disk-Register-Data-Access-Port DKC_REG 95 */ 96 struct hdc9224_UDCreg { /* internal disk controller registers */ 97 u_char udc_dma7; /* 0: DMA address bits 0 - 7 */ 98 u_char udc_dma15; /* 1: DMA address bits 8 - 15 */ 99 u_char udc_dma23; /* 2: DMA address bits 16 - 23 */ 100 u_char udc_dsect; /* 3: desired/starting sector number */ 101 #define udc_csect udc_dsect /* current sector number */ 102 u_char udc_dhead; /* 4: cyl-bits 8-10, desired head number */ 103 #define udc_chead udc_dhead /* current head number */ 104 u_char udc_dcyl; /* 5: desired cylinder number */ 105 #define udc_ccyl udc_dcyl /* current cylinder number */ 106 u_char udc_scnt; /* 6: sector count register */ 107 u_char udc_rtcnt; /* 7: retry count register */ 108 u_char udc_mode; /* 8: operation mode/chip status */ 109 #define udc_cstat udc_mode /* chip status register */ 110 u_char udc_term; /* 9: termination conditions/drive status */ 111 #define udc_dstat udc_term /* drive status register */ 112 u_char udc_data; /* 10: data */ 113 }; 114 115 /* UDC regs */ 116 #define UDC_TERM 9 117 118 /* 119 * Definition of bits in the Current-Head register 120 */ 121 #define UDC_CH_BADSECT (1<<7) /* indicates a bad sector (if bypass=0) */ 122 #define UDC_CH_CYLBITS (0x70) /* bits 10-8 of current cylinder number */ 123 #define UDC_CH_HEADNO (0x0F) /* current head number */ 124 125 /* 126 * Definition of bits in the Retry-Count register 127 */ 128 #define UDC_RC_RTRYCNT (0xF0) /* 1's compl. in read-log, 0 all others */ 129 #define UDC_RC_RXDISAB (1<<3) /* must/should be 0 for normal operation */ 130 #define UDC_RC_INVRDY (1<<2) /* polarity of floppy-status, important! */ 131 #define UDC_RC_MOTOR (1<<1) /* turn on floppy-motor, no effect on HDD */ 132 #define UDC_RC_LOSPEED (1<<0) /* floppy-speed select, RX33: 0, RX50: 1 */ 133 134 #define UDC_RC_HDD_READ 0xF2 /* 0x72 ??? */ 135 #define UDC_RC_HDD_WRT 0xF2 /* 0xF0 ??? */ 136 #define UDC_RC_RX33READ 0x76 /* enable retries when reading floppies */ 137 #define UDC_RC_RX33WRT 0xF6 138 #define UDC_RC_RX50READ 0x77 /* enable retries when reading floppies */ 139 #define UDC_RC_RX50WRT 0xF7 140 141 /* 142 * Definition of bits in the Operating-Mode register 143 */ 144 #define UDC_MD_HDMODE (1<<7) /* must be 1 for all FDD and HDD */ 145 #define UDC_MD_CHKCOD (3<<5) /* error-check: FDD/CRC: 0, HDD/ECC: 1 */ 146 #define UDC_MD_DENS (1<<4) /* density select, must be 0 */ 147 #define UDC_MD_UNUSED (1<<3) /* bit 3 is not used and must be 0 */ 148 #define UDC_MD_SRATE (7<<0) /* seek step rate */ 149 150 #define UDC_MD_HDD 0xC0 151 #define UDC_MD_RX33 0x82 152 #define UDC_MD_RX50 0x81 153 154 /* 155 * Definition of bits in the Chip-Status register 156 */ 157 #define UDC_CS_RETREQ (1<<7) /* retry required */ 158 #define UDC_CS_ECCATT (1<<6) /* error correction attempted */ 159 #define UDC_CS_ECCERR (1<<5) /* ECC/CRC error */ 160 #define UDC_CS_DELDATA (1<<4) /* deleted data mark */ 161 #define UDC_CS_SYNCERR (1<<3) /* synchronization error */ 162 #define UDC_CS_COMPERR (1<<2) /* compare error */ 163 #define UDC_CS_PRESDRV (0x3) /* present drive selected */ 164 165 /* 166 * Definition of bits in the Termination-Conditions register 167 */ 168 #define UDC_TC_CRCPRE (1<<7) /* CRC register preset, must be 1 */ 169 #define UDC_TC_UNUSED (1<<6) /* bit 6 is not used and must be 0 */ 170 #define UDC_TC_INTDONE (1<<5) /* interrupt on done */ 171 #define UDC_TC_TDELDAT (1<<4) /* terminate on deleted data */ 172 #define UDC_TC_TDSTAT3 (1<<3) /* terminate on drive status 3 change */ 173 #define UDC_TC_TWPROT (1<<2) /* terminate on write-protect (FDD only) */ 174 #define UDC_TC_INTRDCH (1<<1) /* interrupt on ready change (FDD only) */ 175 #define UDC_TC_TWRFLT (1<<0) /* interrupt on write-fault (HDD only) */ 176 177 #define UDC_TC_HDD 0xA5 /* 0xB5 ??? */ 178 #define UDC_TC_FDD 0xA0 /* 0xAA ??? 0xB4 ??? */ 179 180 /* 181 * Definition of bits in the Disk-Status register 182 */ 183 #define UDC_DS_SELACK (1<<7) /* select acknowledge (harddisk only!) */ 184 #define UDC_DS_INDEX (1<<6) /* index point */ 185 #define UDC_DS_SKCOM (1<<5) /* seek complete */ 186 #define UDC_DS_TRK00 (1<<4) /* track 0 */ 187 #define UDC_DS_DSTAT3 (1<<3) /* drive status 3 (MBZ) */ 188 #define UDC_DS_WRPROT (1<<2) /* write protect (floppy only!) */ 189 #define UDC_DS_READY (1<<1) /* drive ready bit */ 190 #define UDC_DS_WRFAULT (1<<0) /* write fault */ 191 192 193
Indexes created Wed Sep 24 02:09:48 GMT 2025