1 /* $NetBSD: sysioreg.h,v 1.3 2006/02/11 17:57:32 cdi Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 40 /* 41 * sysio is the sun5/sun4u SBUS controller/DMA/IOMMU/etc. ASIC. 42 */ 43 44 struct sysioreg { 45 struct upareg { 46 uint64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */ 47 uint64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */ 48 } upa; 49 uint64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */ 50 uint64_t pad0; 51 uint64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */ 52 uint64_t reserved; /* 1fe.0000.0028 */ 53 uint64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ 54 uint64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ 55 uint64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */ 56 uint64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */ 57 char pad1[0x2000 - 0x50]; 58 struct sbusreg { 59 uint64_t sys_sbus_cr; /* SBUS Control Register */ /* 1fe.0000.2000 */ 60 uint64_t reserved; /* 1fe.0000.2008 */ 61 uint64_t sys_sbus_afsr; /* SBUS AFSR */ /* 1fe.0000.2010 */ 62 uint64_t sys_sbus_afar; /* SBUS AFAR */ /* 1fe.0000.2018 */ 63 uint64_t sys_sbus_config0; /* SBUS Slot 0 config register */ /* 1fe.0000.2020 */ 64 uint64_t sys_sbus_config1; /* SBUS Slot 1 config register */ /* 1fe.0000.2028 */ 65 uint64_t sys_sbus_config2; /* SBUS Slot 2 config register */ /* 1fe.0000.2030 */ 66 uint64_t sys_sbus_config3; /* SBUS Slot 3 config register */ /* 1fe.0000.2038 */ 67 uint64_t sys_sbus_config13; /* Slot 13 config register <audio> */ /* 1fe.0000.2040 */ 68 uint64_t sys_sbus_config14; /* Slot 14 config register <Macio> */ /* 1fe.0000.2048 */ 69 uint64_t sys_sbus_config15; /* Slot 15 config register <slavio> */ /* 1fe.0000.2050 */ 70 } sbus; 71 char pad2[0x400 - 0x50]; 72 struct iommureg { 73 uint64_t iommu_cr; /* IOMMU control register */ /* 1fe.0000.2400 */ 74 uint64_t iommu_tsb; /* IOMMU TSB base register */ /* 1fe.0000.2408 */ 75 uint64_t iommu_flush; /* IOMMU flush register */ /* 1fe.0000.2410 */ 76 } iommu; 77 uint64_t strbuf_ctl; /* streaming buffer control reg */ /* 1fe.0000.2800 */ 78 uint64_t strbuf_pgflush; /* streaming buffer page flush */ /* 1fe.0000.2808 */ 79 uint64_t strbuf_flushsync; /* streaming buffer flush sync */ /* 1fe.0000.2810 */ 80 81 uint64_t sbus_slot0_int; /* SBUS slot 0 interrupt map reg */ /* 1fe.0000.2c00 */ 82 uint64_t sbus_slot1_int; /* SBUS slot 1 interrupt map reg */ /* 1fe.0000.2c08 */ 83 uint64_t sbus_slot2_int; /* SBUS slot 2 interrupt map reg */ /* 1fe.0000.2c10 */ 84 uint64_t sbus_slot3_int; /* SBUS slot 3 interrupt map reg */ /* 1fe.0000.2c18 */ 85 86 uint64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3000 */ 87 uint64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.3008 */ 88 uint64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.3010 */ 89 uint64_t audio_int_map; /* audio interrupt map reg */ /* 1fe.0000.3018 */ 90 uint64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.3020 */ 91 uint64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.3028 */ 92 uint64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.3030 */ 93 uint64_t therm_int_map; /* thermal warn interrupt map reg */ /* 1fe.0000.3038 */ 94 uint64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.3040 */ 95 uint64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.3048 */ 96 uint64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.3050 */ 97 uint64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.3060 */ 98 uint64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.3068 */ 99 uint64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.3070 */ 100 uint64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.3078 */ 101 uint64_t sbus_int_map; /* SBUS error interrupt map reg */ /* 1fe.0000.3080 */ 102 uint64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.3088 */ 103 uint64_t upagr_int_map; /* UPA graphics interrupt map reg */ /* 1fe.0000.3090 */ 104 uint64_t reserved_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3098 */ 105 106 uint64_t sys_svadiag; /* SBUS virtual addr diag reg */ /* 1fe.0000.4400 */ 107 uint64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */ 108 uint64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.4580-45ff */ 109 uint64_t tlb_data_diag[32]; /* TLB data RAM diag */ /* 1fe.0000.4600-46ff */ 110 uint64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.5000-53f8 */ 111 uint64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.5400-57f8 */ 112 uint64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.5800-5878 */ 113 uint64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.5900-5978 */ 114 }; 115 116 #define IOMMU_CTL_IMPL 0xf0000000 117 #define IOMMU_CTL_VER 0x0f000000 118 #define IOMMU_CTL_RSVD1 0x00ffffe0 119 #define IOMMU_CTL_RANGE 0x0000001c 120 #define IOMMU_CTL_RANGESHFT 2 121 #define IOMMU_CTL_RSVD2 0x00000002 122 #define IOMMU_CTL_ME 0x00000001 123 124 #define IOMMU_BAR_IBA 0xfffffc00 125 #define IOMMU_BAR_IBASHFT 10 126 127 /* Flushpage fields */ 128 #define IOMMU_FLPG_VADDR 0xfffff000 129 #define IOMMU_FLUSH_MASK 0xfffff000 130 131 #define IOMMU_FLUSHPAGE(sc, va) do { \ 132 (sc)->sc_reg->io_flushpage = (va) & IOMMU_FLUSH_MASK; \ 133 } while (0); 134 #define IOMMU_FLUSHALL(sc) do { \ 135 (sc)->sc_reg->io_flashclear = 0; \ 136 } while (0) 137 138 /* to pte.h ? */ 139 typedef uint32_t iopte_t; 140 141 #define IOPTE_PPN 0xffffff00 /* PA<35:12> */ 142 #define IOPTE_C 0x00000080 /* cacheable */ 143 #define IOPTE_W 0x00000004 /* writable */ 144 #define IOPTE_V 0x00000002 /* valid */ 145 #define IOPTE_WAZ 0x00000001 /* must write as zero */ 146 147 #define IOPTE_PPNSHFT 8 /* shift to get ppn from IOPTE */ 148 #define IOPTE_PPNPASHFT 4 /* shift to get pa from ioppn */ 149 150 #define IOPTE_BITS "\20\10C\3W\2V\1WAZ" 151 152
Indexes created Mon Sep 22 05:09:51 GMT 2025