1 /* $NetBSD: ppatomctrl.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef PP_ATOMVOLTAGECTRL_H 27 #define PP_ATOMVOLTAGECTRL_H 28 29 #include "hwmgr.h" 30 31 #define MEM_TYPE_GDDR5 0x50 32 #define MEM_TYPE_GDDR4 0x40 33 #define MEM_TYPE_GDDR3 0x30 34 #define MEM_TYPE_DDR2 0x20 35 #define MEM_TYPE_GDDR1 0x10 36 #define MEM_TYPE_DDR3 0xb0 37 #define MEM_TYPE_MASK 0xF0 38 39 40 /* As returned from PowerConnectorDetectionTable. */ 41 #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80 42 #define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40 43 #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20 44 #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F 45 46 /* New functions for Evergreen and beyond. */ 47 #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32 48 49 struct pp_atomctrl_clock_dividers { 50 uint32_t pll_post_divider; 51 uint32_t pll_feedback_divider; 52 uint32_t pll_ref_divider; 53 bool enable_post_divider; 54 }; 55 56 typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers; 57 58 union pp_atomctrl_tcipll_fb_divider { 59 struct { 60 uint32_t ul_fb_div_frac : 14; 61 uint32_t ul_fb_div : 12; 62 uint32_t un_used : 6; 63 }; 64 uint32_t ul_fb_divider; 65 }; 66 67 typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider; 68 69 struct pp_atomctrl_clock_dividers_rv730 { 70 uint32_t pll_post_divider; 71 pp_atomctrl_tcipll_fb_divider mpll_feedback_divider; 72 uint32_t pll_ref_divider; 73 bool enable_post_divider; 74 bool enable_dithen; 75 uint32_t vco_mode; 76 }; 77 typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730; 78 79 80 struct pp_atomctrl_clock_dividers_kong { 81 uint32_t pll_post_divider; 82 uint32_t real_clock; 83 }; 84 typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong; 85 86 struct pp_atomctrl_clock_dividers_ci { 87 uint32_t pll_post_divider; /* post divider value */ 88 uint32_t real_clock; 89 pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */ 90 uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */ 91 uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */ 92 uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ 93 }; 94 typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci; 95 96 struct pp_atomctrl_clock_dividers_vi { 97 uint32_t pll_post_divider; /* post divider value */ 98 uint32_t real_clock; 99 pp_atomctrl_tcipll_fb_divider ul_fb_div; /*Output Parameter: PLL FB divider */ 100 uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */ 101 uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */ 102 uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ 103 }; 104 typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi; 105 106 struct pp_atomctrl_clock_dividers_ai { 107 u16 usSclk_fcw_frac; 108 u16 usSclk_fcw_int; 109 u8 ucSclkPostDiv; 110 u8 ucSclkVcoMode; 111 u8 ucSclkPllRange; 112 u8 ucSscEnable; 113 u16 usSsc_fcw1_frac; 114 u16 usSsc_fcw1_int; 115 u16 usReserved; 116 u16 usPcc_fcw_int; 117 u16 usSsc_fcw_slew_frac; 118 u16 usPcc_fcw_slew_frac; 119 }; 120 typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai; 121 122 123 union pp_atomctrl_s_mpll_fb_divider { 124 struct { 125 uint32_t cl_kf : 12; 126 uint32_t clk_frac : 12; 127 uint32_t un_used : 8; 128 }; 129 uint32_t ul_fb_divider; 130 }; 131 typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider; 132 133 enum pp_atomctrl_spread_spectrum_mode { 134 pp_atomctrl_spread_spectrum_mode_down = 0, 135 pp_atomctrl_spread_spectrum_mode_center 136 }; 137 typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode; 138 139 struct pp_atomctrl_memory_clock_param { 140 pp_atomctrl_s_mpll_fb_divider mpll_fb_divider; 141 uint32_t mpll_post_divider; 142 uint32_t bw_ctrl; 143 uint32_t dll_speed; 144 uint32_t vco_mode; 145 uint32_t yclk_sel; 146 uint32_t qdr; 147 uint32_t half_rate; 148 }; 149 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param; 150 151 struct pp_atomctrl_memory_clock_param_ai { 152 uint32_t ulClock; 153 uint32_t ulPostDiv; 154 uint16_t ulMclk_fcw_frac; 155 uint16_t ulMclk_fcw_int; 156 }; 157 typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai; 158 159 struct pp_atomctrl_internal_ss_info { 160 uint32_t speed_spectrum_percentage; /* in 1/100 percentage */ 161 uint32_t speed_spectrum_rate; /* in KHz */ 162 pp_atomctrl_spread_spectrum_mode speed_spectrum_mode; 163 }; 164 typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info; 165 166 #ifndef NUMBER_OF_M3ARB_PARAMS 167 #define NUMBER_OF_M3ARB_PARAMS 3 168 #endif 169 170 #ifndef NUMBER_OF_M3ARB_PARAM_SETS 171 #define NUMBER_OF_M3ARB_PARAM_SETS 10 172 #endif 173 174 struct pp_atomctrl_kong_system_info { 175 uint32_t ul_bootup_uma_clock; /* in 10kHz unit */ 176 uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ 177 uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ 178 uint16_t us_bootup_nb_voltage; /* boot up NB voltage */ 179 uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */ 180 uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */ 181 /* 0: default 1: uvd 2: fs-3d */ 182 uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */ 183 }; 184 typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info; 185 186 struct pp_atomctrl_memory_info { 187 uint8_t memory_vendor; 188 uint8_t memory_type; 189 }; 190 typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info; 191 192 #define MAX_AC_TIMING_ENTRIES 16 193 194 struct pp_atomctrl_memory_clock_range_table { 195 uint8_t num_entries; 196 uint8_t rsv[3]; 197 198 uint32_t mclk[MAX_AC_TIMING_ENTRIES]; 199 }; 200 typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table; 201 202 struct pp_atomctrl_voltage_table_entry { 203 uint16_t value; 204 uint32_t smio_low; 205 }; 206 207 typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry; 208 209 struct pp_atomctrl_voltage_table { 210 uint32_t count; 211 uint32_t mask_low; 212 uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */ 213 pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES]; 214 }; 215 216 typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table; 217 218 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 219 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 220 221 struct pp_atomctrl_mc_reg_entry { 222 uint32_t mclk_max; 223 uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 224 }; 225 typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry; 226 227 struct pp_atomctrl_mc_register_address { 228 uint16_t s1; 229 uint8_t uc_pre_reg_data; 230 }; 231 232 typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address; 233 234 #define MAX_SCLK_RANGE 8 235 236 struct pp_atom_ctrl_sclk_range_table_entry{ 237 uint8_t ucVco_setting; 238 uint8_t ucPostdiv; 239 uint16_t usFcw_pcc; 240 uint16_t usFcw_trans_upper; 241 uint16_t usRcw_trans_lower; 242 }; 243 244 245 struct pp_atom_ctrl_sclk_range_table{ 246 struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE]; 247 }; 248 249 struct pp_atomctrl_mc_reg_table { 250 uint8_t last; /* number of registers */ 251 uint8_t num_entries; /* number of AC timing entries */ 252 pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 253 pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 254 }; 255 typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table; 256 257 struct pp_atomctrl_gpio_pin_assignment { 258 uint16_t us_gpio_pin_aindex; 259 uint8_t uc_gpio_pin_bit_shift; 260 }; 261 typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment; 262 263 struct pp_atom_ctrl__avfs_parameters { 264 uint32_t ulAVFS_meanNsigma_Acontant0; 265 uint32_t ulAVFS_meanNsigma_Acontant1; 266 uint32_t ulAVFS_meanNsigma_Acontant2; 267 uint16_t usAVFS_meanNsigma_DC_tol_sigma; 268 uint16_t usAVFS_meanNsigma_Platform_mean; 269 uint16_t usAVFS_meanNsigma_Platform_sigma; 270 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0; 271 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1; 272 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2; 273 uint32_t ulGB_VDROOP_TABLE_CKSON_a0; 274 uint32_t ulGB_VDROOP_TABLE_CKSON_a1; 275 uint32_t ulGB_VDROOP_TABLE_CKSON_a2; 276 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 277 uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2; 278 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b; 279 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1; 280 uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2; 281 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b; 282 uint16_t usMaxVoltage_0_25mv; 283 uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF; 284 uint8_t ucEnableGB_VDROOP_TABLE_CKSON; 285 uint8_t ucEnableGB_FUSE_TABLE_CKSOFF; 286 uint8_t ucEnableGB_FUSE_TABLE_CKSON; 287 uint16_t usPSM_Age_ComFactor; 288 uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage; 289 uint8_t ucReserved; 290 }; 291 292 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); 293 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); 294 extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage); 295 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); 296 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); 297 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); 298 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); 299 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); 300 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); 301 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); 302 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); 303 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); 304 extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); 305 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table); 306 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, 307 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); 308 extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, 309 uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); 310 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, 311 uint32_t clock_value, 312 pp_atomctrl_clock_dividers_kong *dividers); 313 extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, 314 uint16_t end_index, uint32_t mask, uint32_t *efuse); 315 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 316 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); 317 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); 318 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, 319 uint8_t level); 320 extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 321 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); 322 extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); 323 324 extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); 325 326 extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 327 uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, 328 uint16_t *load_line); 329 330 extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, 331 uint16_t *vddc, uint16_t *vddci, 332 uint16_t virtual_voltage_id, 333 uint16_t efuse_voltage_id); 334 extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id); 335 336 extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, 337 uint32_t *min_vddc); 338 #endif 339 340
Indexes created Sat Sep 20 22:09:52 GMT 2025