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      1 // SPDX-License-Identifier: GPL-2.0+
      2 /*
      3  * NXP LPC32xx SoC
      4  *
      5  * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz (a] mleia.com>
      6  * Copyright 2012 Roland Stigge <stigge (a] antcom.de>
      7  */
      8 
      9 #include <dt-bindings/clock/lpc32xx-clock.h>
     10 #include <dt-bindings/interrupt-controller/irq.h>
     11 
     12 / {
     13 	#address-cells = <1>;
     14 	#size-cells = <1>;
     15 	compatible = "nxp,lpc3220";
     16 	interrupt-parent = <&mic>;
     17 
     18 	cpus {
     19 		#address-cells = <1>;
     20 		#size-cells = <0>;
     21 
     22 		cpu@0 {
     23 			compatible = "arm,arm926ej-s";
     24 			device_type = "cpu";
     25 			reg = <0x0>;
     26 		};
     27 	};
     28 
     29 	clocks {
     30 		xtal_32k: xtal_32k {
     31 			compatible = "fixed-clock";
     32 			#clock-cells = <0>;
     33 			clock-frequency = <32768>;
     34 			clock-output-names = "xtal_32k";
     35 		};
     36 
     37 		xtal: xtal {
     38 			compatible = "fixed-clock";
     39 			#clock-cells = <0>;
     40 			clock-frequency = <13000000>;
     41 			clock-output-names = "xtal";
     42 		};
     43 	};
     44 
     45 	ahb {
     46 		#address-cells = <1>;
     47 		#size-cells = <1>;
     48 		compatible = "simple-bus";
     49 		ranges = <0x00000000 0x00000000 0x10000000>,
     50 			 <0x20000000 0x20000000 0x30000000>,
     51 			 <0xe0000000 0xe0000000 0x04000000>;
     52 
     53 		iram: sram@8000000 {
     54 			compatible = "mmio-sram";
     55 			reg = <0x08000000 0x20000>;
     56 
     57 			#address-cells = <1>;
     58 			#size-cells = <1>;
     59 			ranges = <0x00000000 0x08000000 0x20000>;
     60 		};
     61 
     62 		/*
     63 		 * Enable either SLC or MLC
     64 		 */
     65 		slc: flash@20020000 {
     66 			compatible = "nxp,lpc3220-slc";
     67 			reg = <0x20020000 0x1000>;
     68 			clocks = <&clk LPC32XX_CLK_SLC>;
     69 			status = "disabled";
     70 		};
     71 
     72 		mlc: flash@200a8000 {
     73 			compatible = "nxp,lpc3220-mlc";
     74 			reg = <0x200a8000 0x11000>;
     75 			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
     76 			clocks = <&clk LPC32XX_CLK_MLC>;
     77 			status = "disabled";
     78 		};
     79 
     80 		dma: dma@31000000 {
     81 			compatible = "arm,pl080", "arm,primecell";
     82 			reg = <0x31000000 0x1000>;
     83 			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
     84 			clocks = <&clk LPC32XX_CLK_DMA>;
     85 			clock-names = "apb_pclk";
     86 		};
     87 
     88 		usb {
     89 			#address-cells = <1>;
     90 			#size-cells = <1>;
     91 			compatible = "simple-bus";
     92 			ranges = <0x0 0x31020000 0x00001000>;
     93 
     94 			/*
     95 			 * Enable either ohci or usbd (gadget)!
     96 			 */
     97 			ohci: ohci@0 {
     98 				compatible = "nxp,ohci-nxp", "usb-ohci";
     99 				reg = <0x0 0x300>;
    100 				interrupt-parent = <&sic1>;
    101 				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
    102 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
    103 				status = "disabled";
    104 			};
    105 
    106 			usbd: usbd@0 {
    107 				compatible = "nxp,lpc3220-udc";
    108 				reg = <0x0 0x300>;
    109 				interrupt-parent = <&sic1>;
    110 				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
    111 					     <30 IRQ_TYPE_LEVEL_HIGH>,
    112 					     <28 IRQ_TYPE_LEVEL_HIGH>,
    113 					     <26 IRQ_TYPE_LEVEL_LOW>;
    114 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
    115 				status = "disabled";
    116 			};
    117 
    118 			i2cusb: i2c@300 {
    119 				compatible = "nxp,pnx-i2c";
    120 				reg = <0x300 0x100>;
    121 				interrupt-parent = <&sic1>;
    122 				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
    123 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
    124 				#address-cells = <1>;
    125 				#size-cells = <0>;
    126 			};
    127 
    128 			usbclk: clock-controller@f00 {
    129 				compatible = "nxp,lpc3220-usb-clk";
    130 				reg = <0xf00 0x100>;
    131 				#clock-cells = <1>;
    132 			};
    133 		};
    134 
    135 		clcd: clcd@31040000 {
    136 			compatible = "arm,pl111", "arm,primecell";
    137 			reg = <0x31040000 0x1000>;
    138 			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
    139 			clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
    140 			clock-names = "clcdclk", "apb_pclk";
    141 			status = "disabled";
    142 		};
    143 
    144 		mac: ethernet@31060000 {
    145 			compatible = "nxp,lpc-eth";
    146 			reg = <0x31060000 0x1000>;
    147 			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
    148 			clocks = <&clk LPC32XX_CLK_MAC>;
    149 			status = "disabled";
    150 		};
    151 
    152 		emc: memory-controller@31080000 {
    153 			compatible = "arm,pl175", "arm,primecell";
    154 			reg = <0x31080000 0x1000>;
    155 			clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
    156 			clock-names = "mpmcclk", "apb_pclk";
    157 			#address-cells = <1>;
    158 			#size-cells = <1>;
    159 
    160 			ranges = <0 0xe0000000 0x01000000>,
    161 				 <1 0xe1000000 0x01000000>,
    162 				 <2 0xe2000000 0x01000000>,
    163 				 <3 0xe3000000 0x01000000>;
    164 			status = "disabled";
    165 		};
    166 
    167 		apb {
    168 			#address-cells = <1>;
    169 			#size-cells = <1>;
    170 			compatible = "simple-bus";
    171 			ranges = <0x20000000 0x20000000 0x30000000>;
    172 
    173 			/*
    174 			 * ssp0 and spi1 are shared pins;
    175 			 * enable one in your board dts, as needed.
    176 			 */
    177 			ssp0: spi@20084000 {
    178 				compatible = "arm,pl022", "arm,primecell";
    179 				reg = <0x20084000 0x1000>;
    180 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
    181 				clocks = <&clk LPC32XX_CLK_SSP0>;
    182 				clock-names = "apb_pclk";
    183 				#address-cells = <1>;
    184 				#size-cells = <0>;
    185 				status = "disabled";
    186 			};
    187 
    188 			spi1: spi@20088000 {
    189 				compatible = "nxp,lpc3220-spi";
    190 				reg = <0x20088000 0x1000>;
    191 				clocks = <&clk LPC32XX_CLK_SPI1>;
    192 				#address-cells = <1>;
    193 				#size-cells = <0>;
    194 				status = "disabled";
    195 			};
    196 
    197 			/*
    198 			 * ssp1 and spi2 are shared pins;
    199 			 * enable one in your board dts, as needed.
    200 			 */
    201 			ssp1: spi@2008c000 {
    202 				compatible = "arm,pl022", "arm,primecell";
    203 				reg = <0x2008c000 0x1000>;
    204 				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
    205 				clocks = <&clk LPC32XX_CLK_SSP1>;
    206 				clock-names = "apb_pclk";
    207 				#address-cells = <1>;
    208 				#size-cells = <0>;
    209 				status = "disabled";
    210 			};
    211 
    212 			spi2: spi@20090000 {
    213 				compatible = "nxp,lpc3220-spi";
    214 				reg = <0x20090000 0x1000>;
    215 				clocks = <&clk LPC32XX_CLK_SPI2>;
    216 				#address-cells = <1>;
    217 				#size-cells = <0>;
    218 				status = "disabled";
    219 			};
    220 
    221 			i2s0: i2s@20094000 {
    222 				compatible = "nxp,lpc3220-i2s";
    223 				reg = <0x20094000 0x1000>;
    224 				status = "disabled";
    225 			};
    226 
    227 			sd: sd@20098000 {
    228 				compatible = "arm,pl18x", "arm,primecell";
    229 				reg = <0x20098000 0x1000>;
    230 				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
    231 					     <13 IRQ_TYPE_LEVEL_HIGH>;
    232 				clocks = <&clk LPC32XX_CLK_SD>;
    233 				clock-names = "apb_pclk";
    234 				status = "disabled";
    235 			};
    236 
    237 			i2s1: i2s@2009c000 {
    238 				compatible = "nxp,lpc3220-i2s";
    239 				reg = <0x2009c000 0x1000>;
    240 				status = "disabled";
    241 			};
    242 
    243 			/* UART5 first since it is the default console, ttyS0 */
    244 			uart5: serial@40090000 {
    245 				/* actually, ns16550a w/ 64 byte fifos! */
    246 				compatible = "nxp,lpc3220-uart";
    247 				reg = <0x40090000 0x1000>;
    248 				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
    249 				reg-shift = <2>;
    250 				clocks = <&clk LPC32XX_CLK_UART5>;
    251 				status = "disabled";
    252 			};
    253 
    254 			uart3: serial@40080000 {
    255 				compatible = "nxp,lpc3220-uart";
    256 				reg = <0x40080000 0x1000>;
    257 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    258 				reg-shift = <2>;
    259 				clocks = <&clk LPC32XX_CLK_UART3>;
    260 				status = "disabled";
    261 			};
    262 
    263 			uart4: serial@40088000 {
    264 				compatible = "nxp,lpc3220-uart";
    265 				reg = <0x40088000 0x1000>;
    266 				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
    267 				reg-shift = <2>;
    268 				clocks = <&clk LPC32XX_CLK_UART4>;
    269 				status = "disabled";
    270 			};
    271 
    272 			uart6: serial@40098000 {
    273 				compatible = "nxp,lpc3220-uart";
    274 				reg = <0x40098000 0x1000>;
    275 				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
    276 				reg-shift = <2>;
    277 				clocks = <&clk LPC32XX_CLK_UART6>;
    278 				status = "disabled";
    279 			};
    280 
    281 			i2c1: i2c@400a0000 {
    282 				compatible = "nxp,pnx-i2c";
    283 				reg = <0x400a0000 0x100>;
    284 				interrupt-parent = <&sic1>;
    285 				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
    286 				#address-cells = <1>;
    287 				#size-cells = <0>;
    288 				clocks = <&clk LPC32XX_CLK_I2C1>;
    289 			};
    290 
    291 			i2c2: i2c@400a8000 {
    292 				compatible = "nxp,pnx-i2c";
    293 				reg = <0x400a8000 0x100>;
    294 				interrupt-parent = <&sic1>;
    295 				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
    296 				#address-cells = <1>;
    297 				#size-cells = <0>;
    298 				clocks = <&clk LPC32XX_CLK_I2C2>;
    299 			};
    300 
    301 			mpwm: mpwm@400e8000 {
    302 				compatible = "nxp,lpc3220-motor-pwm";
    303 				reg = <0x400e8000 0x78>;
    304 				status = "disabled";
    305 				#pwm-cells = <2>;
    306 			};
    307 		};
    308 
    309 		fab {
    310 			#address-cells = <1>;
    311 			#size-cells = <1>;
    312 			compatible = "simple-bus";
    313 			ranges = <0x20000000 0x20000000 0x30000000>;
    314 
    315 			/* System Control Block */
    316 			scb {
    317 				compatible = "simple-bus";
    318 				ranges = <0x0 0x040004000 0x00001000>;
    319 				#address-cells = <1>;
    320 				#size-cells = <1>;
    321 
    322 				clk: clock-controller@0 {
    323 					compatible = "nxp,lpc3220-clk";
    324 					reg = <0x00 0x114>;
    325 					#clock-cells = <1>;
    326 
    327 					clocks = <&xtal_32k>, <&xtal>;
    328 					clock-names = "xtal_32k", "xtal";
    329 				};
    330 			};
    331 
    332 			mic: interrupt-controller@40008000 {
    333 				compatible = "nxp,lpc3220-mic";
    334 				reg = <0x40008000 0x4000>;
    335 				interrupt-controller;
    336 				#interrupt-cells = <2>;
    337 			};
    338 
    339 			sic1: interrupt-controller@4000c000 {
    340 				compatible = "nxp,lpc3220-sic";
    341 				reg = <0x4000c000 0x4000>;
    342 				interrupt-controller;
    343 				#interrupt-cells = <2>;
    344 
    345 				interrupt-parent = <&mic>;
    346 				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
    347 					     <30 IRQ_TYPE_LEVEL_LOW>;
    348 				};
    349 
    350 			sic2: interrupt-controller@40010000 {
    351 				compatible = "nxp,lpc3220-sic";
    352 				reg = <0x40010000 0x4000>;
    353 				interrupt-controller;
    354 				#interrupt-cells = <2>;
    355 
    356 				interrupt-parent = <&mic>;
    357 				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
    358 					     <31 IRQ_TYPE_LEVEL_LOW>;
    359 			};
    360 
    361 			uart1: serial@40014000 {
    362 				compatible = "nxp,lpc3220-hsuart";
    363 				reg = <0x40014000 0x1000>;
    364 				interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
    365 				status = "disabled";
    366 			};
    367 
    368 			uart2: serial@40018000 {
    369 				compatible = "nxp,lpc3220-hsuart";
    370 				reg = <0x40018000 0x1000>;
    371 				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
    372 				status = "disabled";
    373 			};
    374 
    375 			uart7: serial@4001c000 {
    376 				compatible = "nxp,lpc3220-hsuart";
    377 				reg = <0x4001c000 0x1000>;
    378 				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
    379 				status = "disabled";
    380 			};
    381 
    382 			rtc: rtc@40024000 {
    383 				compatible = "nxp,lpc3220-rtc";
    384 				reg = <0x40024000 0x1000>;
    385 				interrupt-parent = <&sic1>;
    386 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
    387 				clocks = <&clk LPC32XX_CLK_RTC>;
    388 			};
    389 
    390 			gpio: gpio@40028000 {
    391 				compatible = "nxp,lpc3220-gpio";
    392 				reg = <0x40028000 0x1000>;
    393 				gpio-controller;
    394 				#gpio-cells = <3>; /* bank, pin, flags */
    395 			};
    396 
    397 			timer4: timer@4002c000 {
    398 				compatible = "nxp,lpc3220-timer";
    399 				reg = <0x4002c000 0x1000>;
    400 				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
    401 				clocks = <&clk LPC32XX_CLK_TIMER4>;
    402 				clock-names = "timerclk";
    403 				status = "disabled";
    404 			};
    405 
    406 			timer5: timer@40030000 {
    407 				compatible = "nxp,lpc3220-timer";
    408 				reg = <0x40030000 0x1000>;
    409 				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
    410 				clocks = <&clk LPC32XX_CLK_TIMER5>;
    411 				clock-names = "timerclk";
    412 				status = "disabled";
    413 			};
    414 
    415 			watchdog: watchdog@4003c000 {
    416 				compatible = "nxp,pnx4008-wdt";
    417 				reg = <0x4003c000 0x1000>;
    418 				clocks = <&clk LPC32XX_CLK_WDOG>;
    419 			};
    420 
    421 			timer0: timer@40044000 {
    422 				compatible = "nxp,lpc3220-timer";
    423 				reg = <0x40044000 0x1000>;
    424 				clocks = <&clk LPC32XX_CLK_TIMER0>;
    425 				clock-names = "timerclk";
    426 				interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
    427 			};
    428 
    429 			/*
    430 			 * TSC vs. ADC: Since those two share the same
    431 			 * hardware, you need to choose from one of the
    432 			 * following two and do 'status = "okay";' for one of
    433 			 * them
    434 			 */
    435 
    436 			adc: adc@40048000 {
    437 				compatible = "nxp,lpc3220-adc";
    438 				reg = <0x40048000 0x1000>;
    439 				interrupt-parent = <&sic1>;
    440 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    441 				clocks = <&clk LPC32XX_CLK_ADC>;
    442 				status = "disabled";
    443 			};
    444 
    445 			tsc: tsc@40048000 {
    446 				compatible = "nxp,lpc3220-tsc";
    447 				reg = <0x40048000 0x1000>;
    448 				interrupt-parent = <&sic1>;
    449 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    450 				clocks = <&clk LPC32XX_CLK_ADC>;
    451 				status = "disabled";
    452 			};
    453 
    454 			timer1: timer@4004c000 {
    455 				compatible = "nxp,lpc3220-timer";
    456 				reg = <0x4004c000 0x1000>;
    457 				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
    458 				clocks = <&clk LPC32XX_CLK_TIMER1>;
    459 				clock-names = "timerclk";
    460 			};
    461 
    462 			key: key@40050000 {
    463 				compatible = "nxp,lpc3220-key";
    464 				reg = <0x40050000 0x1000>;
    465 				clocks = <&clk LPC32XX_CLK_KEY>;
    466 				interrupt-parent = <&sic1>;
    467 				interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
    468 				status = "disabled";
    469 			};
    470 
    471 			timer2: timer@40058000 {
    472 				compatible = "nxp,lpc3220-timer";
    473 				reg = <0x40058000 0x1000>;
    474 				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
    475 				clocks = <&clk LPC32XX_CLK_TIMER2>;
    476 				clock-names = "timerclk";
    477 				status = "disabled";
    478 			};
    479 
    480 			pwm1: pwm@4005c000 {
    481 				compatible = "nxp,lpc3220-pwm";
    482 				reg = <0x4005c000 0x4>;
    483 				clocks = <&clk LPC32XX_CLK_PWM1>;
    484 				assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
    485 				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
    486 				status = "disabled";
    487 			};
    488 
    489 			pwm2: pwm@4005c004 {
    490 				compatible = "nxp,lpc3220-pwm";
    491 				reg = <0x4005c004 0x4>;
    492 				clocks = <&clk LPC32XX_CLK_PWM2>;
    493 				assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
    494 				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
    495 				status = "disabled";
    496 			};
    497 
    498 			timer3: timer@40060000 {
    499 				compatible = "nxp,lpc3220-timer";
    500 				reg = <0x40060000 0x1000>;
    501 				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
    502 				clocks = <&clk LPC32XX_CLK_TIMER3>;
    503 				clock-names = "timerclk";
    504 				status = "disabled";
    505 			};
    506 		};
    507 	};
    508 };
    509