1 /* $NetBSD: amdgpu_uvd_v4_2.c,v 1.6 2021/12/19 00:25:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian Knig <christian.koenig (at) amd.com> 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v4_2.c,v 1.6 2021/12/19 00:25:04 riastradh Exp $"); 29 30 #include <linux/firmware.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_uvd.h" 34 #include "cikd.h" 35 36 #include "uvd/uvd_4_2_d.h" 37 #include "uvd/uvd_4_2_sh_mask.h" 38 39 #include "oss/oss_2_0_d.h" 40 #include "oss/oss_2_0_sh_mask.h" 41 42 #include "bif/bif_4_1_d.h" 43 44 #include "smu/smu_7_0_1_d.h" 45 #include "smu/smu_7_0_1_sh_mask.h" 46 47 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 48 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 49 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 50 static int uvd_v4_2_start(struct amdgpu_device *adev); 51 static void uvd_v4_2_stop(struct amdgpu_device *adev); 52 static int uvd_v4_2_set_clockgating_state(void *handle, 53 enum amd_clockgating_state state); 54 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 55 bool sw_mode); 56 /** 57 * uvd_v4_2_ring_get_rptr - get read pointer 58 * 59 * @ring: amdgpu_ring pointer 60 * 61 * Returns the current hardware read pointer 62 */ 63 static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 return RREG32(mmUVD_RBC_RB_RPTR); 68 } 69 70 /** 71 * uvd_v4_2_ring_get_wptr - get write pointer 72 * 73 * @ring: amdgpu_ring pointer 74 * 75 * Returns the current hardware write pointer 76 */ 77 static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 78 { 79 struct amdgpu_device *adev = ring->adev; 80 81 return RREG32(mmUVD_RBC_RB_WPTR); 82 } 83 84 /** 85 * uvd_v4_2_ring_set_wptr - set write pointer 86 * 87 * @ring: amdgpu_ring pointer 88 * 89 * Commits the write pointer to the hardware 90 */ 91 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 92 { 93 struct amdgpu_device *adev = ring->adev; 94 95 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 96 } 97 98 static int uvd_v4_2_early_init(void *handle) 99 { 100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 101 adev->uvd.num_uvd_inst = 1; 102 103 uvd_v4_2_set_ring_funcs(adev); 104 uvd_v4_2_set_irq_funcs(adev); 105 106 return 0; 107 } 108 109 static int uvd_v4_2_sw_init(void *handle) 110 { 111 struct amdgpu_ring *ring; 112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 113 int r; 114 115 /* UVD TRAP */ 116 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); 117 if (r) 118 return r; 119 120 r = amdgpu_uvd_sw_init(adev); 121 if (r) 122 return r; 123 124 ring = &adev->uvd.inst->ring; 125 snprintf(ring->name, sizeof ring->name, "uvd"); 126 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 127 if (r) 128 return r; 129 130 r = amdgpu_uvd_resume(adev); 131 if (r) 132 return r; 133 134 r = amdgpu_uvd_entity_init(adev); 135 136 return r; 137 } 138 139 static int uvd_v4_2_sw_fini(void *handle) 140 { 141 int r; 142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 143 144 r = amdgpu_uvd_suspend(adev); 145 if (r) 146 return r; 147 148 return amdgpu_uvd_sw_fini(adev); 149 } 150 151 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 152 bool enable); 153 /** 154 * uvd_v4_2_hw_init - start and test UVD block 155 * 156 * @adev: amdgpu_device pointer 157 * 158 * Initialize the hardware, boot up the VCPU and do some testing 159 */ 160 static int uvd_v4_2_hw_init(void *handle) 161 { 162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 164 uint32_t tmp; 165 int r; 166 167 uvd_v4_2_enable_mgcg(adev, true); 168 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 169 170 r = amdgpu_ring_test_helper(ring); 171 if (r) 172 goto done; 173 174 r = amdgpu_ring_alloc(ring, 10); 175 if (r) { 176 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 177 goto done; 178 } 179 180 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 181 amdgpu_ring_write(ring, tmp); 182 amdgpu_ring_write(ring, 0xFFFFF); 183 184 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 185 amdgpu_ring_write(ring, tmp); 186 amdgpu_ring_write(ring, 0xFFFFF); 187 188 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 189 amdgpu_ring_write(ring, tmp); 190 amdgpu_ring_write(ring, 0xFFFFF); 191 192 /* Clear timeout status bits */ 193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 194 amdgpu_ring_write(ring, 0x8); 195 196 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 197 amdgpu_ring_write(ring, 3); 198 199 amdgpu_ring_commit(ring); 200 201 done: 202 if (!r) 203 DRM_INFO("UVD initialized successfully.\n"); 204 205 return r; 206 } 207 208 /** 209 * uvd_v4_2_hw_fini - stop the hardware block 210 * 211 * @adev: amdgpu_device pointer 212 * 213 * Stop the UVD block, mark ring as not ready any more 214 */ 215 static int uvd_v4_2_hw_fini(void *handle) 216 { 217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 219 220 if (RREG32(mmUVD_STATUS) != 0) 221 uvd_v4_2_stop(adev); 222 223 ring->sched.ready = false; 224 225 return 0; 226 } 227 228 static int uvd_v4_2_suspend(void *handle) 229 { 230 int r; 231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 232 233 r = uvd_v4_2_hw_fini(adev); 234 if (r) 235 return r; 236 237 return amdgpu_uvd_suspend(adev); 238 } 239 240 static int uvd_v4_2_resume(void *handle) 241 { 242 int r; 243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 244 245 r = amdgpu_uvd_resume(adev); 246 if (r) 247 return r; 248 249 return uvd_v4_2_hw_init(adev); 250 } 251 252 /** 253 * uvd_v4_2_start - start UVD block 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Setup and start the UVD block 258 */ 259 static int uvd_v4_2_start(struct amdgpu_device *adev) 260 { 261 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 262 uint32_t rb_bufsz; 263 int i, j, r; 264 u32 tmp; 265 /* disable byte swapping */ 266 u32 lmi_swap_cntl = 0; 267 u32 mp_swap_cntl = 0; 268 269 /* set uvd busy */ 270 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); 271 272 uvd_v4_2_set_dcm(adev, true); 273 WREG32(mmUVD_CGC_GATE, 0); 274 275 /* take UVD block out of reset */ 276 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 277 mdelay(5); 278 279 /* enable VCPU clock */ 280 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 281 282 /* disable interupt */ 283 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 284 285 #ifdef __BIG_ENDIAN 286 /* swap (8 in 32) RB and IB */ 287 lmi_swap_cntl = 0xa; 288 mp_swap_cntl = 0; 289 #endif 290 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 291 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 292 /* initialize UVD memory controller */ 293 WREG32(mmUVD_LMI_CTRL, 0x203108); 294 295 tmp = RREG32(mmUVD_MPC_CNTL); 296 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); 297 298 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 299 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 300 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 301 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 302 WREG32(mmUVD_MPC_SET_ALU, 0); 303 WREG32(mmUVD_MPC_SET_MUX, 0x88); 304 305 uvd_v4_2_mc_resume(adev); 306 307 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); 308 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); 309 310 /* enable UMC */ 311 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 312 313 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 314 315 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 316 317 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 318 319 mdelay(10); 320 321 for (i = 0; i < 10; ++i) { 322 uint32_t status; 323 for (j = 0; j < 100; ++j) { 324 status = RREG32(mmUVD_STATUS); 325 if (status & 2) 326 break; 327 mdelay(10); 328 } 329 r = 0; 330 if (status & 2) 331 break; 332 333 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 334 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 335 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 336 mdelay(10); 337 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 338 mdelay(10); 339 r = -1; 340 } 341 342 if (r) { 343 DRM_ERROR("UVD not responding, giving up!!!\n"); 344 return r; 345 } 346 347 /* enable interupt */ 348 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 349 350 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); 351 352 /* force RBC into idle state */ 353 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 354 355 /* Set the write pointer delay */ 356 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 357 358 /* programm the 4GB memory segment for rptr and ring buffer */ 359 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 360 (0x7 << 16) | (0x1 << 31)); 361 362 /* Initialize the ring buffer's read and write pointers */ 363 WREG32(mmUVD_RBC_RB_RPTR, 0x0); 364 365 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 366 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 367 368 /* set the ring address */ 369 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 370 371 /* Set ring buffer size */ 372 rb_bufsz = order_base_2(ring->ring_size); 373 rb_bufsz = (0x1 << 8) | rb_bufsz; 374 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 375 376 return 0; 377 } 378 379 /** 380 * uvd_v4_2_stop - stop UVD block 381 * 382 * @adev: amdgpu_device pointer 383 * 384 * stop the UVD block 385 */ 386 static void uvd_v4_2_stop(struct amdgpu_device *adev) 387 { 388 uint32_t i, j; 389 uint32_t status; 390 391 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 392 393 for (i = 0; i < 10; ++i) { 394 for (j = 0; j < 100; ++j) { 395 status = RREG32(mmUVD_STATUS); 396 if (status & 2) 397 break; 398 mdelay(1); 399 } 400 if (status & 2) 401 break; 402 } 403 404 for (i = 0; i < 10; ++i) { 405 for (j = 0; j < 100; ++j) { 406 status = RREG32(mmUVD_LMI_STATUS); 407 if (status & 0xf) 408 break; 409 mdelay(1); 410 } 411 if (status & 0xf) 412 break; 413 } 414 415 /* Stall UMC and register bus before resetting VCPU */ 416 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 417 418 for (i = 0; i < 10; ++i) { 419 for (j = 0; j < 100; ++j) { 420 status = RREG32(mmUVD_LMI_STATUS); 421 if (status & 0x240) 422 break; 423 mdelay(1); 424 } 425 if (status & 0x240) 426 break; 427 } 428 429 WREG32_P(0x3D49, 0, ~(1 << 2)); 430 431 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); 432 433 /* put LMI, VCPU, RBC etc... into reset */ 434 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 435 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 436 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 437 438 WREG32(mmUVD_STATUS, 0); 439 440 uvd_v4_2_set_dcm(adev, false); 441 } 442 443 /** 444 * uvd_v4_2_ring_emit_fence - emit an fence & trap command 445 * 446 * @ring: amdgpu_ring pointer 447 * @fence: fence to emit 448 * 449 * Write a fence and a trap command to the ring. 450 */ 451 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 452 unsigned flags) 453 { 454 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 455 456 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 457 amdgpu_ring_write(ring, seq); 458 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 459 amdgpu_ring_write(ring, addr & 0xffffffff); 460 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 461 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 462 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 463 amdgpu_ring_write(ring, 0); 464 465 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 466 amdgpu_ring_write(ring, 0); 467 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 468 amdgpu_ring_write(ring, 0); 469 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 470 amdgpu_ring_write(ring, 2); 471 } 472 473 /** 474 * uvd_v4_2_ring_test_ring - register write test 475 * 476 * @ring: amdgpu_ring pointer 477 * 478 * Test if we can successfully write to the context register 479 */ 480 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 481 { 482 struct amdgpu_device *adev = ring->adev; 483 uint32_t tmp = 0; 484 unsigned i; 485 int r; 486 487 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 488 r = amdgpu_ring_alloc(ring, 3); 489 if (r) 490 return r; 491 492 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 493 amdgpu_ring_write(ring, 0xDEADBEEF); 494 amdgpu_ring_commit(ring); 495 for (i = 0; i < adev->usec_timeout; i++) { 496 tmp = RREG32(mmUVD_CONTEXT_ID); 497 if (tmp == 0xDEADBEEF) 498 break; 499 udelay(1); 500 } 501 502 if (i >= adev->usec_timeout) 503 r = -ETIMEDOUT; 504 505 return r; 506 } 507 508 /** 509 * uvd_v4_2_ring_emit_ib - execute indirect buffer 510 * 511 * @ring: amdgpu_ring pointer 512 * @ib: indirect buffer to execute 513 * 514 * Write ring commands to execute the indirect buffer 515 */ 516 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 517 struct amdgpu_job *job, 518 struct amdgpu_ib *ib, 519 uint32_t flags) 520 { 521 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 522 amdgpu_ring_write(ring, ib->gpu_addr); 523 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 524 amdgpu_ring_write(ring, ib->length_dw); 525 } 526 527 static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 528 { 529 int i; 530 531 WARN_ON(ring->wptr % 2 || count % 2); 532 533 for (i = 0; i < count / 2; i++) { 534 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 535 amdgpu_ring_write(ring, 0); 536 } 537 } 538 539 /** 540 * uvd_v4_2_mc_resume - memory controller programming 541 * 542 * @adev: amdgpu_device pointer 543 * 544 * Let the UVD memory controller know it's offsets 545 */ 546 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 547 { 548 uint64_t addr; 549 uint32_t size; 550 551 /* programm the VCPU memory controller bits 0-27 */ 552 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 553 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; 554 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 555 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 556 557 addr += size; 558 size = AMDGPU_UVD_HEAP_SIZE >> 3; 559 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 560 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 561 562 addr += size; 563 size = (AMDGPU_UVD_STACK_SIZE + 564 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 565 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 566 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 567 568 /* bits 28-31 */ 569 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; 570 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 571 572 /* bits 32-39 */ 573 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; 574 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 575 576 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 577 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 578 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 579 } 580 581 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 582 bool enable) 583 { 584 u32 orig, data; 585 586 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 587 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 588 data |= 0xfff; 589 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 590 591 orig = data = RREG32(mmUVD_CGC_CTRL); 592 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 593 if (orig != data) 594 WREG32(mmUVD_CGC_CTRL, data); 595 } else { 596 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 597 data &= ~0xfff; 598 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 599 600 orig = data = RREG32(mmUVD_CGC_CTRL); 601 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 602 if (orig != data) 603 WREG32(mmUVD_CGC_CTRL, data); 604 } 605 } 606 607 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 608 bool sw_mode) 609 { 610 u32 tmp, tmp2; 611 612 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); 613 614 tmp = RREG32(mmUVD_CGC_CTRL); 615 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 616 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 617 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 618 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 619 620 if (sw_mode) { 621 tmp &= ~0x7ffff800; 622 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 623 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 624 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 625 } else { 626 tmp |= 0x7ffff800; 627 tmp2 = 0; 628 } 629 630 WREG32(mmUVD_CGC_CTRL, tmp); 631 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 632 } 633 634 static bool uvd_v4_2_is_idle(void *handle) 635 { 636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 637 638 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 639 } 640 641 static int uvd_v4_2_wait_for_idle(void *handle) 642 { 643 unsigned i; 644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 645 646 for (i = 0; i < adev->usec_timeout; i++) { 647 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 648 return 0; 649 } 650 return -ETIMEDOUT; 651 } 652 653 static int uvd_v4_2_soft_reset(void *handle) 654 { 655 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 656 657 uvd_v4_2_stop(adev); 658 659 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 660 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 661 mdelay(5); 662 663 return uvd_v4_2_start(adev); 664 } 665 666 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 667 struct amdgpu_irq_src *source, 668 unsigned type, 669 enum amdgpu_interrupt_state state) 670 { 671 // TODO 672 return 0; 673 } 674 675 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 676 struct amdgpu_irq_src *source, 677 struct amdgpu_iv_entry *entry) 678 { 679 DRM_DEBUG("IH: UVD TRAP\n"); 680 amdgpu_fence_process(&adev->uvd.inst->ring); 681 return 0; 682 } 683 684 static int uvd_v4_2_set_clockgating_state(void *handle, 685 enum amd_clockgating_state state) 686 { 687 return 0; 688 } 689 690 static int uvd_v4_2_set_powergating_state(void *handle, 691 enum amd_powergating_state state) 692 { 693 /* This doesn't actually powergate the UVD block. 694 * That's done in the dpm code via the SMC. This 695 * just re-inits the block as necessary. The actual 696 * gating still happens in the dpm code. We should 697 * revisit this when there is a cleaner line between 698 * the smc and the hw blocks 699 */ 700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 701 702 if (state == AMD_PG_STATE_GATE) { 703 uvd_v4_2_stop(adev); 704 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 705 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 706 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK)) { 707 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 708 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK | 709 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 710 mdelay(20); 711 } 712 } 713 return 0; 714 } else { 715 if (adev->pg_flags & AMD_PG_SUPPORT_UVD && !adev->pm.dpm_enabled) { 716 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 717 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 718 WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK | 719 UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK | 720 UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK)); 721 mdelay(30); 722 } 723 } 724 return uvd_v4_2_start(adev); 725 } 726 } 727 728 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 729 .name = "uvd_v4_2", 730 .early_init = uvd_v4_2_early_init, 731 .late_init = NULL, 732 .sw_init = uvd_v4_2_sw_init, 733 .sw_fini = uvd_v4_2_sw_fini, 734 .hw_init = uvd_v4_2_hw_init, 735 .hw_fini = uvd_v4_2_hw_fini, 736 .suspend = uvd_v4_2_suspend, 737 .resume = uvd_v4_2_resume, 738 .is_idle = uvd_v4_2_is_idle, 739 .wait_for_idle = uvd_v4_2_wait_for_idle, 740 .soft_reset = uvd_v4_2_soft_reset, 741 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 742 .set_powergating_state = uvd_v4_2_set_powergating_state, 743 }; 744 745 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 746 .type = AMDGPU_RING_TYPE_UVD, 747 .align_mask = 0xf, 748 .support_64bit_ptrs = false, 749 .no_user_fence = true, 750 .get_rptr = uvd_v4_2_ring_get_rptr, 751 .get_wptr = uvd_v4_2_ring_get_wptr, 752 .set_wptr = uvd_v4_2_ring_set_wptr, 753 .parse_cs = amdgpu_uvd_ring_parse_cs, 754 .emit_frame_size = 755 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 756 .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 757 .emit_ib = uvd_v4_2_ring_emit_ib, 758 .emit_fence = uvd_v4_2_ring_emit_fence, 759 .test_ring = uvd_v4_2_ring_test_ring, 760 .test_ib = amdgpu_uvd_ring_test_ib, 761 .insert_nop = uvd_v4_2_ring_insert_nop, 762 .pad_ib = amdgpu_ring_generic_pad_ib, 763 .begin_use = amdgpu_uvd_ring_begin_use, 764 .end_use = amdgpu_uvd_ring_end_use, 765 }; 766 767 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 768 { 769 adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs; 770 } 771 772 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 773 .set = uvd_v4_2_set_interrupt_state, 774 .process = uvd_v4_2_process_interrupt, 775 }; 776 777 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 778 { 779 adev->uvd.inst->irq.num_types = 1; 780 adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs; 781 } 782 783 const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 784 { 785 .type = AMD_IP_BLOCK_TYPE_UVD, 786 .major = 4, 787 .minor = 2, 788 .rev = 0, 789 .funcs = &uvd_v4_2_ip_funcs, 790 }; 791
Indexes created Fri Sep 26 08:10:20 GMT 2025