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    Searched defs:v16i8 (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
657 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
659 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
690 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }
1628 {ISD::ADD, MVT::v16i8, 1}, member in class:MVT
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 470 {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 3},
471 {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 3},
472 {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1},
473 {ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1},
501 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i8, 3},
502 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i8, 1},
595 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
596 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
599 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
1159 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}
1603 {ISD::ADD, MVT::v16i8, 1}, member in class:MVT
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
677 { ISD::SHL, MVT::v16i8, 1 },
678 { ISD::SRL, MVT::v16i8, 2 },
679 { ISD::SRA, MVT::v16i8, 2 }
1494 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, member in class:MVT
1507 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, member in class:MVT
1514 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, \/\/ widen to zmm member in class:MVT
1521 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, \/\/ widen to zmm member in class:MVT
1669 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, member in class:MVT
1680 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, member in class:MVT
1684 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, member in class:MVT
1691 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, \/\/ vpsllw+vptestmb member in class:MVT
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/Headers/
msa.h 14 typedef signed char v16i8 __attribute__((vector_size(16), aligned(16))); typedef
  /src/external/gpl3/gcc/dist/gcc/config/mips/
msa.h 31 typedef signed char v16i8 __attribute__ ((vector_size(16), aligned(16))); typedef
  /src/external/gpl3/gcc.old/dist/gcc/config/mips/
msa.h 31 typedef signed char v16i8 __attribute__ ((vector_size(16), aligned(16))); typedef
  /src/external/gpl3/gcc/dist/gcc/config/loongarch/
lsxintrin.h 30 typedef signed char v16i8 __attribute__ ((vector_size(16), aligned(16))); typedef
60 return (__m128i)__builtin_lsx_vsll_b ((v16i8)_1, (v16i8)_2);
90 ((__m128i)__builtin_lsx_vslli_b ((v16i8)(_1), (_2)))
112 return (__m128i)__builtin_lsx_vsra_b ((v16i8)_1, (v16i8)_2);
142 ((__m128i)__builtin_lsx_vsrai_b ((v16i8)(_1), (_2)))
164 return (__m128i)__builtin_lsx_vsrar_b ((v16i8)_1, (v16i8)_2);
194 ((__m128i)__builtin_lsx_vsrari_b ((v16i8)(_1), (_2))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 715 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
764 // We promote all shuffles to v16i8.
766 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
841 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
871 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
875 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
884 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
922 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
927 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
946 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal)
2297 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); member in class:MVT
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