| /src/sys/crypto/blake2/ |
| blake2s.c | 94 uint32_t v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12,v13,v14,v15; local in function:blake2s_compress
104 v5 = h[5];
130 BLAKE2S_G(v1, v5, v9, v13, m[sigma[ 2]], m[sigma[ 3]]);
133 BLAKE2S_G(v0, v5, v10, v15, m[sigma[ 8]], m[sigma[ 9]]);
145 h[5] ^= v5 ^ v13;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_crtc.c | 469 PIXEL_CLOCK_PARAMETERS_V5 v5; member in union:set_pixel_clock
498 args.v5.ucCRTC = ATOM_CRTC_INVALID;
499 args.v5.usPixelClock = cpu_to_le16(dispclk);
500 args.v5.ucPpll = ATOM_DCPLL;
650 args.v5.ucCRTC = crtc_id;
651 args.v5.usPixelClock = cpu_to_le16(clock / 10);
652 args.v5.ucRefDiv = ref_div;
653 args.v5.usFbDiv = cpu_to_le16(fb_div);
654 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
655 args.v5.ucPostDiv = post_div
[all...] |
| amdgpu_atombios_encoders.c | 574 DIG_ENCODER_CONTROL_PARAMETERS_V5 v5; member in union:dig_encoder_control
705 args.v5.asDPPanelModeParam.ucAction = action;
706 args.v5.asDPPanelModeParam.ucPanelMode = panel_mode;
707 args.v5.asDPPanelModeParam.ucDigId = dig->dig_encoder;
710 args.v5.asStreamParam.ucAction = action;
711 args.v5.asStreamParam.ucDigId = dig->dig_encoder;
712 args.v5.asStreamParam.ucDigMode =
714 if (ENCODER_MODE_IS_DP(args.v5.asStreamParam.ucDigMode))
715 args.v5.asStreamParam.ucLaneNum = dp_lane_count;
718 args.v5.asStreamParam.ucLaneNum = 8
762 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; member in union:dig_transmitter_control
[all...] |
| amdgpu_atombios.c | 998 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; member in union:get_clock_dividers
1044 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1046 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1050 dividers->post_div = args.v5.ucPostDiv;
1051 dividers->enable_post_div = (args.v5.ucCntlFlag &
1053 dividers->enable_dithen = (args.v5.ucCntlFlag &
1055 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1056 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1057 dividers->ref_div = args.v5.ucRefDiv;
1058 dividers->vco_mode = (args.v5.ucCntlFlag
[all...] |
| /src/lib/libm/src/ |
| e_lgammaf_r.c | 70 v5 = 3.2170924824e-03, /* 0x3b52d5db */ variable in typeref:typename:const float
202 p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));
|
| e_lgamma_r.c | 134 v5 = 3.21709242282423911810e-03, /* 0x3F6A5ABB, 0x57D0CF61 */ variable in typeref:typename:const double
266 p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));
|
| /src/sys/external/bsd/compiler_rt/dist/lib/tsan/rtl/ |
| tsan_ppc_regs.h | 70 #define v5 5 macro
|
| /src/lib/libm/ld80/ |
| e_lgammal_r.c | 144 #define v5 (v5u.extu_ld) macro
320 p2 = 1+y*(v1+y*(v2+y*(v3+y*(v4+y*(v5+y*v6)))));
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_crtc.c | 772 PIXEL_CLOCK_PARAMETERS_V5 v5; member in union:set_pixel_clock
800 args.v5.ucCRTC = ATOM_CRTC_INVALID;
801 args.v5.usPixelClock = cpu_to_le16(dispclk);
802 args.v5.ucPpll = ATOM_DCPLL;
896 args.v5.ucCRTC = crtc_id;
897 args.v5.usPixelClock = cpu_to_le16(clock / 10);
898 args.v5.ucRefDiv = ref_div;
899 args.v5.usFbDiv = cpu_to_le16(fb_div);
900 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
901 args.v5.ucPostDiv = post_div
[all...] |
| radeon_atombios_encoders.c | 1017 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; member in union:dig_transmitter_control
1318 args.v5.ucAction = action;
1320 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1322 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1327 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1333 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1335 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1339 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1341 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE
[all...] |
| radeon_atombios.c | 2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; member in union:get_clock_dividers
2899 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2901 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2905 dividers->post_div = args.v5.ucPostDiv;
2906 dividers->enable_post_div = (args.v5.ucCntlFlag &
2908 dividers->enable_dithen = (args.v5.ucCntlFlag &
2910 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2911 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2912 dividers->ref_div = args.v5.ucRefDiv;
2913 dividers->vco_mode = (args.v5.ucCntlFlag
[all...] |
| /src/lib/libm/ld128/ |
| e_lgammal_r.c | 122 v5 = 5.14448694179047879915042998453632434e+00L, variable in typeref:typename:const long double
291 p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*(v5+y*(v6+y*(v7+
|
| /src/sys/dev/pci/ixgbe/ |
| ixv.c | 1287 u64 v0, v1, v2, v3, v4, v5, v6, v7; local in function:ixv_handle_timer
1303 v0 = v1 = v2 = v3 = v4 = v5 = v6 = v7 = 0;
1313 v5 += txr->q_eagain_tx_dma_setup;
1322 IXGBE_EVC_STORE(&sc->eagain_tx_dma_setup, v5);
|
| ixgbe.c | 4618 u64 v0, v1, v2, v3, v4, v5, v6, v7; local in function:ixgbe_handle_timer
4657 v0 = v1 = v2 = v3 = v4 = v5 = v6 = v7 = 0;
4667 v5 += txr->q_eagain_tx_dma_setup;
4676 IXGBE_EVC_STORE(&sc->eagain_tx_dma_setup, v5);
|
| /src/sys/dev/ic/ |
| bwfmreg.h | 526 } v5; member in union:bwfm_sta_info::__anonb4efa704020a
|
