1 /* $NetBSD: dcn10_optc.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_TIMING_GENERATOR_DCN10_H__ 29 #define __DC_TIMING_GENERATOR_DCN10_H__ 30 31 #include "timing_generator.h" 32 33 #define DCN10TG_FROM_TG(tg)\ 34 container_of(tg, struct optc, base) 35 36 #define TG_COMMON_REG_LIST_DCN(inst) \ 37 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 38 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 39 SRI(OTG_VREADY_PARAM, OTG, inst),\ 40 SRI(OTG_BLANK_CONTROL, OTG, inst),\ 41 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 42 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 43 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 44 SRI(OTG_H_TOTAL, OTG, inst),\ 45 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 46 SRI(OTG_H_SYNC_A, OTG, inst),\ 47 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ 48 SRI(OTG_H_TIMING_CNTL, OTG, inst),\ 49 SRI(OTG_V_TOTAL, OTG, inst),\ 50 SRI(OTG_V_BLANK_START_END, OTG, inst),\ 51 SRI(OTG_V_SYNC_A, OTG, inst),\ 52 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ 53 SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ 54 SRI(OTG_CONTROL, OTG, inst),\ 55 SRI(OTG_STEREO_CONTROL, OTG, inst),\ 56 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ 57 SRI(OTG_STEREO_STATUS, OTG, inst),\ 58 SRI(OTG_V_TOTAL_MAX, OTG, inst),\ 59 SRI(OTG_V_TOTAL_MID, OTG, inst),\ 60 SRI(OTG_V_TOTAL_MIN, OTG, inst),\ 61 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ 62 SRI(OTG_TRIGA_CNTL, OTG, inst),\ 63 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ 64 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ 65 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ 66 SRI(OTG_STATUS, OTG, inst),\ 67 SRI(OTG_STATUS_POSITION, OTG, inst),\ 68 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ 69 SRI(OTG_BLACK_COLOR, OTG, inst),\ 70 SRI(OTG_CLOCK_CONTROL, OTG, inst),\ 71 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ 72 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ 73 SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ 74 SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ 75 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ 76 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ 77 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ 78 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ 79 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ 80 SRI(CONTROL, VTG, inst),\ 81 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ 82 SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ 83 SRI(OTG_GSL_CONTROL, OTG, inst),\ 84 SRI(OTG_CRC_CNTL, OTG, inst),\ 85 SRI(OTG_CRC0_DATA_RG, OTG, inst),\ 86 SRI(OTG_CRC0_DATA_B, OTG, inst),\ 87 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ 88 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ 89 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ 90 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ 91 SR(GSL_SOURCE_SELECT),\ 92 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 93 SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) 94 95 #define TG_COMMON_REG_LIST_DCN1_0(inst) \ 96 TG_COMMON_REG_LIST_DCN(inst),\ 97 SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ 98 SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ 99 SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ 100 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) 101 102 103 struct dcn_optc_registers { 104 uint32_t OTG_GLOBAL_CONTROL1; 105 uint32_t OTG_GLOBAL_CONTROL2; 106 uint32_t OTG_VERT_SYNC_CONTROL; 107 uint32_t OTG_MASTER_UPDATE_MODE; 108 uint32_t OTG_GSL_CONTROL; 109 uint32_t OTG_VSTARTUP_PARAM; 110 uint32_t OTG_VUPDATE_PARAM; 111 uint32_t OTG_VREADY_PARAM; 112 uint32_t OTG_BLANK_CONTROL; 113 uint32_t OTG_MASTER_UPDATE_LOCK; 114 uint32_t OTG_GLOBAL_CONTROL0; 115 uint32_t OTG_DOUBLE_BUFFER_CONTROL; 116 uint32_t OTG_H_TOTAL; 117 uint32_t OTG_H_BLANK_START_END; 118 uint32_t OTG_H_SYNC_A; 119 uint32_t OTG_H_SYNC_A_CNTL; 120 uint32_t OTG_H_TIMING_CNTL; 121 uint32_t OTG_V_TOTAL; 122 uint32_t OTG_V_BLANK_START_END; 123 uint32_t OTG_V_SYNC_A; 124 uint32_t OTG_V_SYNC_A_CNTL; 125 uint32_t OTG_INTERLACE_CONTROL; 126 uint32_t OTG_CONTROL; 127 uint32_t OTG_STEREO_CONTROL; 128 uint32_t OTG_3D_STRUCTURE_CONTROL; 129 uint32_t OTG_STEREO_STATUS; 130 uint32_t OTG_V_TOTAL_MAX; 131 uint32_t OTG_V_TOTAL_MID; 132 uint32_t OTG_V_TOTAL_MIN; 133 uint32_t OTG_V_TOTAL_CONTROL; 134 uint32_t OTG_TRIGA_CNTL; 135 uint32_t OTG_TRIGA_MANUAL_TRIG; 136 uint32_t OTG_MANUAL_FLOW_CONTROL; 137 uint32_t OTG_FORCE_COUNT_NOW_CNTL; 138 uint32_t OTG_STATIC_SCREEN_CONTROL; 139 uint32_t OTG_STATUS_FRAME_COUNT; 140 uint32_t OTG_STATUS; 141 uint32_t OTG_STATUS_POSITION; 142 uint32_t OTG_NOM_VERT_POSITION; 143 uint32_t OTG_BLACK_COLOR; 144 uint32_t OTG_TEST_PATTERN_PARAMETERS; 145 uint32_t OTG_TEST_PATTERN_CONTROL; 146 uint32_t OTG_TEST_PATTERN_COLOR; 147 uint32_t OTG_CLOCK_CONTROL; 148 uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; 149 uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; 150 uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; 151 uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; 152 uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; 153 uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; 154 uint32_t OPTC_INPUT_CLOCK_CONTROL; 155 uint32_t OPTC_DATA_SOURCE_SELECT; 156 uint32_t OPTC_MEMORY_CONFIG; 157 uint32_t OPTC_INPUT_GLOBAL_CONTROL; 158 uint32_t CONTROL; 159 uint32_t OTG_GSL_WINDOW_X; 160 uint32_t OTG_GSL_WINDOW_Y; 161 uint32_t OTG_VUPDATE_KEEPOUT; 162 uint32_t OTG_CRC_CNTL; 163 uint32_t OTG_CRC0_DATA_RG; 164 uint32_t OTG_CRC0_DATA_B; 165 uint32_t OTG_CRC0_WINDOWA_X_CONTROL; 166 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; 167 uint32_t OTG_CRC0_WINDOWB_X_CONTROL; 168 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; 169 uint32_t GSL_SOURCE_SELECT; 170 uint32_t DWB_SOURCE_SELECT; 171 uint32_t OTG_DSC_START_POSITION; 172 uint32_t OPTC_DATA_FORMAT_CONTROL; 173 uint32_t OPTC_BYTES_PER_PIXEL; 174 uint32_t OPTC_WIDTH_CONTROL; 175 }; 176 177 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ 178 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 179 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 180 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 181 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 182 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ 183 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ 184 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ 185 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 186 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 187 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 188 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 189 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ 190 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 191 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 192 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 193 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 194 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 195 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 196 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ 197 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 198 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 199 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 200 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 201 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 202 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 203 SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ 204 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 205 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 206 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 207 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 208 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 209 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 210 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 211 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 212 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 213 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 214 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 215 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 216 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 217 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 218 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 219 SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ 220 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 221 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 222 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 223 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 224 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ 225 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 226 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ 227 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ 228 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 229 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 230 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 231 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 232 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 233 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 234 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 235 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ 236 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ 237 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ 238 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ 239 SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ 240 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 241 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 242 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 243 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 244 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 245 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 246 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 247 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 248 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ 249 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ 250 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ 251 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 252 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 253 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 254 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 255 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 256 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 257 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 258 SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ 259 SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ 260 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 261 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 262 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 263 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 264 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 265 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 266 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 267 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 268 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 269 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 270 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 271 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 272 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 273 SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ 274 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 275 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 276 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 277 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 278 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 279 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 280 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 281 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 282 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 283 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 284 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 285 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 286 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 287 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 288 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 289 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 290 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 291 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 292 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 293 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ 294 SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ 295 SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ 296 SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ 297 SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) 298 299 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 300 TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ 301 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ 302 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ 303 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ 304 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ 305 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ 306 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ 307 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ 308 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ 309 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ 310 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ 311 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ 312 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ 313 SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ 314 315 #define TG_REG_FIELD_LIST_DCN1_0(type) \ 316 type VSTARTUP_START;\ 317 type VUPDATE_OFFSET;\ 318 type VUPDATE_WIDTH;\ 319 type VREADY_OFFSET;\ 320 type OTG_BLANK_DATA_EN;\ 321 type OTG_BLANK_DE_MODE;\ 322 type OTG_CURRENT_BLANK_STATE;\ 323 type OTG_MASTER_UPDATE_LOCK;\ 324 type UPDATE_LOCK_STATUS;\ 325 type OTG_UPDATE_PENDING;\ 326 type OTG_MASTER_UPDATE_LOCK_SEL;\ 327 type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ 328 type OTG_H_TOTAL;\ 329 type OTG_H_BLANK_START;\ 330 type OTG_H_BLANK_END;\ 331 type OTG_H_SYNC_A_START;\ 332 type OTG_H_SYNC_A_END;\ 333 type OTG_H_SYNC_A_POL;\ 334 type OTG_H_TIMING_DIV_BY2;\ 335 type OTG_V_TOTAL;\ 336 type OTG_V_BLANK_START;\ 337 type OTG_V_BLANK_END;\ 338 type OTG_V_SYNC_A_START;\ 339 type OTG_V_SYNC_A_END;\ 340 type OTG_V_SYNC_A_POL;\ 341 type OTG_INTERLACE_ENABLE;\ 342 type OTG_MASTER_EN;\ 343 type OTG_START_POINT_CNTL;\ 344 type OTG_DISABLE_POINT_CNTL;\ 345 type OTG_FIELD_NUMBER_CNTL;\ 346 type OTG_STEREO_EN;\ 347 type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ 348 type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ 349 type OTG_STEREO_EYE_FLAG_POLARITY;\ 350 type OTG_STEREO_CURRENT_EYE;\ 351 type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ 352 type OTG_3D_STRUCTURE_EN;\ 353 type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ 354 type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ 355 type OTG_V_TOTAL_MAX;\ 356 type OTG_V_TOTAL_MID;\ 357 type OTG_V_TOTAL_MIN;\ 358 type OTG_V_TOTAL_MIN_SEL;\ 359 type OTG_V_TOTAL_MAX_SEL;\ 360 type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ 361 type OTG_VTOTAL_MID_FRAME_NUM;\ 362 type OTG_FORCE_LOCK_ON_EVENT;\ 363 type OTG_SET_V_TOTAL_MIN_MASK_EN;\ 364 type OTG_SET_V_TOTAL_MIN_MASK;\ 365 type OTG_FORCE_COUNT_NOW_CLEAR;\ 366 type OTG_FORCE_COUNT_NOW_MODE;\ 367 type OTG_FORCE_COUNT_NOW_OCCURRED;\ 368 type OTG_TRIGA_SOURCE_SELECT;\ 369 type OTG_TRIGA_SOURCE_PIPE_SELECT;\ 370 type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ 371 type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ 372 type OTG_TRIGA_POLARITY_SELECT;\ 373 type OTG_TRIGA_FREQUENCY_SELECT;\ 374 type OTG_TRIGA_DELAY;\ 375 type OTG_TRIGA_CLEAR;\ 376 type OTG_TRIGA_MANUAL_TRIG;\ 377 type OTG_STATIC_SCREEN_EVENT_MASK;\ 378 type OTG_STATIC_SCREEN_FRAME_COUNT;\ 379 type OTG_FRAME_COUNT;\ 380 type OTG_V_BLANK;\ 381 type OTG_V_ACTIVE_DISP;\ 382 type OTG_HORZ_COUNT;\ 383 type OTG_VERT_COUNT;\ 384 type OTG_VERT_COUNT_NOM;\ 385 type OTG_BLACK_COLOR_B_CB;\ 386 type OTG_BLACK_COLOR_G_Y;\ 387 type OTG_BLACK_COLOR_R_CR;\ 388 type OTG_TEST_PATTERN_INC0;\ 389 type OTG_TEST_PATTERN_INC1;\ 390 type OTG_TEST_PATTERN_VRES;\ 391 type OTG_TEST_PATTERN_HRES;\ 392 type OTG_TEST_PATTERN_RAMP0_OFFSET;\ 393 type OTG_TEST_PATTERN_EN;\ 394 type OTG_TEST_PATTERN_MODE;\ 395 type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ 396 type OTG_TEST_PATTERN_COLOR_FORMAT;\ 397 type OTG_TEST_PATTERN_MASK;\ 398 type OTG_TEST_PATTERN_DATA;\ 399 type OTG_BUSY;\ 400 type OTG_CLOCK_EN;\ 401 type OTG_CLOCK_ON;\ 402 type OTG_CLOCK_GATE_DIS;\ 403 type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ 404 type OTG_VERTICAL_INTERRUPT0_LINE_START;\ 405 type OTG_VERTICAL_INTERRUPT0_LINE_END;\ 406 type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\ 407 type OTG_VERTICAL_INTERRUPT1_LINE_START;\ 408 type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ 409 type OTG_VERTICAL_INTERRUPT2_LINE_START;\ 410 type OPTC_INPUT_CLK_EN;\ 411 type OPTC_INPUT_CLK_ON;\ 412 type OPTC_INPUT_CLK_GATE_DIS;\ 413 type OPTC_UNDERFLOW_OCCURRED_STATUS;\ 414 type OPTC_UNDERFLOW_CLEAR;\ 415 type OPTC_SRC_SEL;\ 416 type VTG0_ENABLE;\ 417 type VTG0_FP2;\ 418 type VTG0_VCOUNT_INIT;\ 419 type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ 420 type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ 421 type OTG_AUTO_FORCE_VSYNC_MODE;\ 422 type MASTER_UPDATE_INTERLACED_MODE;\ 423 type OTG_GSL0_EN;\ 424 type OTG_GSL1_EN;\ 425 type OTG_GSL2_EN;\ 426 type OTG_GSL_MASTER_EN;\ 427 type OTG_GSL_FORCE_DELAY;\ 428 type OTG_GSL_CHECK_ALL_FIELDS;\ 429 type OTG_GSL_WINDOW_START_X;\ 430 type OTG_GSL_WINDOW_END_X;\ 431 type OTG_GSL_WINDOW_START_Y;\ 432 type OTG_GSL_WINDOW_END_Y;\ 433 type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ 434 type OTG_GSL_MASTER_MODE;\ 435 type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ 436 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ 437 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ 438 type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ 439 type OTG_CRC_CONT_EN;\ 440 type OTG_CRC0_SELECT;\ 441 type OTG_CRC_EN;\ 442 type CRC0_R_CR;\ 443 type CRC0_G_Y;\ 444 type CRC0_B_CB;\ 445 type OTG_CRC0_WINDOWA_X_START;\ 446 type OTG_CRC0_WINDOWA_X_END;\ 447 type OTG_CRC0_WINDOWA_Y_START;\ 448 type OTG_CRC0_WINDOWA_Y_END;\ 449 type OTG_CRC0_WINDOWB_X_START;\ 450 type OTG_CRC0_WINDOWB_X_END;\ 451 type OTG_CRC0_WINDOWB_Y_START;\ 452 type OTG_CRC0_WINDOWB_Y_END;\ 453 type GSL0_READY_SOURCE_SEL;\ 454 type GSL1_READY_SOURCE_SEL;\ 455 type GSL2_READY_SOURCE_SEL;\ 456 type MANUAL_FLOW_CONTROL;\ 457 type MANUAL_FLOW_CONTROL_SEL; 458 459 460 #define TG_REG_FIELD_LIST(type) \ 461 TG_REG_FIELD_LIST_DCN1_0(type)\ 462 type MASTER_UPDATE_LOCK_DB_X;\ 463 type MASTER_UPDATE_LOCK_DB_Y;\ 464 type MASTER_UPDATE_LOCK_DB_EN;\ 465 type GLOBAL_UPDATE_LOCK_EN;\ 466 type DIG_UPDATE_LOCATION;\ 467 type OTG_DSC_START_POSITION_X;\ 468 type OTG_DSC_START_POSITION_LINE_NUM;\ 469 type OPTC_NUM_OF_INPUT_SEGMENT;\ 470 type OPTC_SEG0_SRC_SEL;\ 471 type OPTC_SEG1_SRC_SEL;\ 472 type OPTC_MEM_SEL;\ 473 type OPTC_DATA_FORMAT;\ 474 type OPTC_DSC_MODE;\ 475 type OPTC_DSC_BYTES_PER_PIXEL;\ 476 type OPTC_DSC_SLICE_WIDTH;\ 477 type OPTC_SEGMENT_WIDTH;\ 478 type OPTC_DWB0_SOURCE_SELECT;\ 479 type OPTC_DWB1_SOURCE_SELECT; 480 481 482 483 struct dcn_optc_shift { 484 TG_REG_FIELD_LIST(uint8_t) 485 }; 486 487 struct dcn_optc_mask { 488 TG_REG_FIELD_LIST(uint32_t) 489 }; 490 491 struct optc { 492 struct timing_generator base; 493 494 const struct dcn_optc_registers *tg_regs; 495 const struct dcn_optc_shift *tg_shift; 496 const struct dcn_optc_mask *tg_mask; 497 498 int opp_count; 499 500 uint32_t max_h_total; 501 uint32_t max_v_total; 502 503 uint32_t min_h_blank; 504 505 uint32_t min_h_sync_width; 506 uint32_t min_v_sync_width; 507 uint32_t min_v_blank; 508 uint32_t min_v_blank_interlace; 509 510 int vstartup_start; 511 int vupdate_offset; 512 int vupdate_width; 513 int vready_offset; 514 enum signal_type signal; 515 }; 516 517 void dcn10_timing_generator_init(struct optc *optc); 518 519 struct dcn_otg_state { 520 uint32_t v_blank_start; 521 uint32_t v_blank_end; 522 uint32_t v_sync_a_pol; 523 uint32_t v_total; 524 uint32_t v_total_max; 525 uint32_t v_total_min; 526 uint32_t v_total_min_sel; 527 uint32_t v_total_max_sel; 528 uint32_t v_sync_a_start; 529 uint32_t v_sync_a_end; 530 uint32_t h_blank_start; 531 uint32_t h_blank_end; 532 uint32_t h_sync_a_start; 533 uint32_t h_sync_a_end; 534 uint32_t h_sync_a_pol; 535 uint32_t h_total; 536 uint32_t underflow_occurred_status; 537 uint32_t otg_enabled; 538 uint32_t blank_enabled; 539 }; 540 541 void optc1_read_otg_state(struct optc *optc1, 542 struct dcn_otg_state *s); 543 544 bool optc1_get_hw_timing(struct timing_generator *tg, 545 struct dc_crtc_timing *hw_crtc_timing); 546 547 bool optc1_validate_timing( 548 struct timing_generator *optc, 549 const struct dc_crtc_timing *timing); 550 551 void optc1_program_timing( 552 struct timing_generator *optc, 553 const struct dc_crtc_timing *dc_crtc_timing, 554 int vready_offset, 555 int vstartup_start, 556 int vupdate_offset, 557 int vupdate_width, 558 const enum signal_type signal, 559 bool use_vbios); 560 561 void optc1_setup_vertical_interrupt0( 562 struct timing_generator *optc, 563 uint32_t start_line, 564 uint32_t end_line); 565 void optc1_setup_vertical_interrupt1( 566 struct timing_generator *optc, 567 uint32_t start_line); 568 void optc1_setup_vertical_interrupt2( 569 struct timing_generator *optc, 570 uint32_t start_line); 571 572 void optc1_program_global_sync( 573 struct timing_generator *optc, 574 int vready_offset, 575 int vstartup_start, 576 int vupdate_offset, 577 int vupdate_width); 578 579 bool optc1_disable_crtc(struct timing_generator *optc); 580 581 bool optc1_is_counter_moving(struct timing_generator *optc); 582 583 void optc1_get_position(struct timing_generator *optc, 584 struct crtc_position *position); 585 586 uint32_t optc1_get_vblank_counter(struct timing_generator *optc); 587 588 void optc1_get_crtc_scanoutpos( 589 struct timing_generator *optc, 590 uint32_t *v_blank_start, 591 uint32_t *v_blank_end, 592 uint32_t *h_position, 593 uint32_t *v_position); 594 595 void optc1_set_early_control( 596 struct timing_generator *optc, 597 uint32_t early_cntl); 598 599 void optc1_wait_for_state(struct timing_generator *optc, 600 enum crtc_state state); 601 602 void optc1_set_blank(struct timing_generator *optc, 603 bool enable_blanking); 604 605 bool optc1_is_blanked(struct timing_generator *optc); 606 607 void optc1_program_blank_color( 608 struct timing_generator *optc, 609 const struct tg_color *black_color); 610 611 bool optc1_did_triggered_reset_occur( 612 struct timing_generator *optc); 613 614 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); 615 616 void optc1_disable_reset_trigger(struct timing_generator *optc); 617 618 void optc1_lock(struct timing_generator *optc); 619 620 void optc1_unlock(struct timing_generator *optc); 621 622 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); 623 624 void optc1_set_drr( 625 struct timing_generator *optc, 626 const struct drr_params *params); 627 628 void optc1_set_static_screen_control( 629 struct timing_generator *optc, 630 uint32_t event_triggers, 631 uint32_t num_frames); 632 633 void optc1_program_stereo(struct timing_generator *optc, 634 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 635 636 bool optc1_is_stereo_left_eye(struct timing_generator *optc); 637 638 void optc1_clear_optc_underflow(struct timing_generator *optc); 639 640 void optc1_tg_init(struct timing_generator *optc); 641 642 bool optc1_is_tg_enabled(struct timing_generator *optc); 643 644 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); 645 646 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); 647 648 bool optc1_get_otg_active_size(struct timing_generator *optc, 649 uint32_t *otg_active_width, 650 uint32_t *otg_active_height); 651 652 void optc1_enable_crtc_reset( 653 struct timing_generator *optc, 654 int source_tg_inst, 655 struct crtc_trigger_info *crtc_tp); 656 657 bool optc1_configure_crc(struct timing_generator *optc, 658 const struct crc_params *params); 659 660 bool optc1_get_crc(struct timing_generator *optc, 661 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 662 663 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); 664 665 void optc1_set_vtg_params(struct timing_generator *optc, 666 const struct dc_crtc_timing *dc_crtc_timing); 667 668 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ 669
Indexes created Sun Sep 21 16:09:51 GMT 2025