/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
hwmgr_ppt.h | 62 uint32_t vclk; /* UVD V-clock */ member in struct:phm_ppt_v1_mm_clock_voltage_dependency_record
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amdgpu_smu8_hwmgr.c | 147 if (clock <= ptable->entries[i].vclk) 155 if (clock >= ptable->entries[i].vclk) 518 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; 602 clock = table->entries[level].vclk; 604 clock = table->entries[table->count - 1].vclk; 1393 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; 1697 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; local in function:smu8_read_sensor 1731 vclk = uvd_table->entries[uvd_index].vclk; [all...] |
smu10_hwmgr.h | 99 uint32_t vclk; member in struct:smu10_uvd_clocks
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smu7_hwmgr.h | 70 uint32_t vclk; member in struct:smu7_uvd_clocks
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smu8_hwmgr.h | 116 uint32_t vclk; member in struct:smu8_uvd_clocks
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vega10_hwmgr.h | 98 uint32_t vclk; member in struct:vega10_uvd_clocks
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vega20_hwmgr.h | 115 uint32_t vclk; member in struct:vega20_uvd_clocks
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/src/sys/external/bsd/drm2/dist/drm/radeon/ |
trinity_dpm.h | 71 u32 vclk; member in struct:trinity_uvd_clock_table_entry
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radeon.h | 1385 u32 vclk; member in struct:radeon_ps 1471 u32 vclk; member in struct:radeon_uvd_clock_voltage_dependency_entry 1742 unsigned vclk, unsigned dclk, 2007 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
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/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
power_state.h | 145 uint32_t VCLK; 185 unsigned long vclk; member in struct:pp_clock_engine_request
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amdgpu_smu.h | 133 uint32_t vclk; member in struct:smu_uvd_clocks 219 uint32_t vclk; member in struct:smu_bios_boot_up_values
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hwmgr.h | 111 uint32_t vclk; member in struct:phm_uvdclock_voltage_dependency_record 138 uint32_t vclk; member in struct:phm_uvd_clock_voltage_dependency_record
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/src/sys/dev/pci/ |
pm2fb.c | 1565 uint32_t vclk, tmp; local in function:pm2fb_set_dac 1605 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL); 1607 vclk & 0xfffffffc); 1643 uint32_t vclk; local in function:pm2vfb_set_dac 1684 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM2_VCLKCTL); 1686 vclk & 0xfffffffc);
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pm3fb.c | 1378 uint32_t vclk, tmp1; local in function:pm3fb_set_mode 1422 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_V_CLOCK_CTL); 1423 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_V_CLOCK_CTL, (vclk & 0xFFFFFFFC));
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radeonfb.c | 2194 /* put vclk into reset, use atomic updates */ 2244 /* put vclk into reset, use atomic updates */ 2883 uint32_t vclk; local in function:radeonfb_putpal 2900 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2902 vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2920 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk);
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/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_dpm.h | 62 u32 vclk; member in struct:amdgpu_ps 164 u32 vclk; member in struct:amdgpu_uvd_clock_voltage_dependency_entry
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