1 /* $NetBSD: amdgpu_vega10_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vega10_smumgr.c,v 1.2 2021/12/18 23:45:27 riastradh Exp $"); 28 29 #include <linux/pci.h> 30 31 #include "smumgr.h" 32 #include "vega10_inc.h" 33 #include "soc15_common.h" 34 #include "vega10_smumgr.h" 35 #include "vega10_hwmgr.h" 36 #include "vega10_ppsmc.h" 37 #include "smu9_driver_if.h" 38 #include "smu9_smumgr.h" 39 #include "ppatomctrl.h" 40 #include "pp_debug.h" 41 42 43 static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, 44 uint8_t *table, int16_t table_id) 45 { 46 struct vega10_smumgr *priv = hwmgr->smu_backend; 47 struct amdgpu_device *adev = hwmgr->adev; 48 49 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 50 "Invalid SMU Table ID!", return -EINVAL); 51 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, 52 "Invalid SMU Table version!", return -EINVAL); 53 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, 54 "Invalid SMU Table Length!", return -EINVAL); 55 smu9_send_msg_to_smc_with_parameter(hwmgr, 56 PPSMC_MSG_SetDriverDramAddrHigh, 57 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); 58 smu9_send_msg_to_smc_with_parameter(hwmgr, 59 PPSMC_MSG_SetDriverDramAddrLow, 60 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); 61 smu9_send_msg_to_smc_with_parameter(hwmgr, 62 PPSMC_MSG_TransferTableSmu2Dram, 63 priv->smu_tables.entry[table_id].table_id); 64 65 /* flush hdp cache */ 66 amdgpu_asic_flush_hdp(adev, NULL); 67 68 memcpy(table, priv->smu_tables.entry[table_id].table, 69 priv->smu_tables.entry[table_id].size); 70 71 return 0; 72 } 73 74 static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, 75 uint8_t *table, int16_t table_id) 76 { 77 struct vega10_smumgr *priv = hwmgr->smu_backend; 78 struct amdgpu_device *adev = hwmgr->adev; 79 80 /* under sriov, vbios or hypervisor driver 81 * has already copy table to smc so here only skip it 82 */ 83 if (!hwmgr->not_vf) 84 return 0; 85 86 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, 87 "Invalid SMU Table ID!", return -EINVAL); 88 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, 89 "Invalid SMU Table version!", return -EINVAL); 90 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, 91 "Invalid SMU Table Length!", return -EINVAL); 92 93 memcpy(priv->smu_tables.entry[table_id].table, table, 94 priv->smu_tables.entry[table_id].size); 95 96 amdgpu_asic_flush_hdp(adev, NULL); 97 98 smu9_send_msg_to_smc_with_parameter(hwmgr, 99 PPSMC_MSG_SetDriverDramAddrHigh, 100 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); 101 smu9_send_msg_to_smc_with_parameter(hwmgr, 102 PPSMC_MSG_SetDriverDramAddrLow, 103 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); 104 smu9_send_msg_to_smc_with_parameter(hwmgr, 105 PPSMC_MSG_TransferTableDram2Smu, 106 priv->smu_tables.entry[table_id].table_id); 107 108 return 0; 109 } 110 111 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr, 112 bool enable, uint32_t feature_mask) 113 { 114 int msg = enable ? PPSMC_MSG_EnableSmuFeatures : 115 PPSMC_MSG_DisableSmuFeatures; 116 117 /* VF has no permission to change smu feature due 118 * to security concern even under pp one vf mode 119 * it still can't do it. For vega10, the smu in 120 * vbios will enable the appropriate features. 121 * */ 122 if (!hwmgr->not_vf) 123 return 0; 124 125 return smum_send_msg_to_smc_with_parameter(hwmgr, 126 msg, feature_mask); 127 } 128 129 int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr, 130 uint64_t *features_enabled) 131 { 132 if (features_enabled == NULL) 133 return -EINVAL; 134 135 smu9_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures); 136 *features_enabled = smu9_get_argument(hwmgr); 137 138 return 0; 139 } 140 141 static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr) 142 { 143 uint64_t features_enabled = 0; 144 145 vega10_get_enabled_smc_features(hwmgr, &features_enabled); 146 147 if (features_enabled & SMC_DPM_FEATURES) 148 return true; 149 else 150 return false; 151 } 152 153 static int vega10_set_tools_address(struct pp_hwmgr *hwmgr) 154 { 155 struct vega10_smumgr *priv = hwmgr->smu_backend; 156 157 if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) { 158 smu9_send_msg_to_smc_with_parameter(hwmgr, 159 PPSMC_MSG_SetToolsDramAddrHigh, 160 upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr)); 161 smu9_send_msg_to_smc_with_parameter(hwmgr, 162 PPSMC_MSG_SetToolsDramAddrLow, 163 lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr)); 164 } 165 return 0; 166 } 167 168 static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) 169 { 170 uint32_t smc_driver_if_version; 171 struct amdgpu_device *adev = hwmgr->adev; 172 uint32_t dev_id; 173 uint32_t rev_id; 174 175 PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr, 176 PPSMC_MSG_GetDriverIfVersion), 177 "Attempt to get SMC IF Version Number Failed!", 178 return -EINVAL); 179 smc_driver_if_version = smu9_get_argument(hwmgr); 180 181 dev_id = adev->pdev->device; 182 rev_id = adev->pdev->revision; 183 184 if (!((dev_id == 0x687f) && 185 ((rev_id == 0xc0) || 186 (rev_id == 0xc1) || 187 (rev_id == 0xc3)))) { 188 if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) { 189 pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n", 190 smc_driver_if_version, SMU9_DRIVER_IF_VERSION); 191 return -EINVAL; 192 } 193 } 194 195 return 0; 196 } 197 198 static int vega10_smu_init(struct pp_hwmgr *hwmgr) 199 { 200 struct vega10_smumgr *priv; 201 unsigned long tools_size; 202 int ret; 203 struct cgs_firmware_info info = {0}; 204 205 ret = cgs_get_firmware_info(hwmgr->device, 206 CGS_UCODE_ID_SMU, 207 &info); 208 if (ret || !info.kptr) 209 return -EINVAL; 210 211 priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL); 212 213 if (!priv) 214 return -ENOMEM; 215 216 hwmgr->smu_backend = priv; 217 218 /* allocate space for pptable */ 219 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev, 220 sizeof(PPTable_t), 221 PAGE_SIZE, 222 AMDGPU_GEM_DOMAIN_VRAM, 223 &priv->smu_tables.entry[PPTABLE].handle, 224 &priv->smu_tables.entry[PPTABLE].mc_addr, 225 &priv->smu_tables.entry[PPTABLE].table); 226 if (ret) 227 goto free_backend; 228 229 priv->smu_tables.entry[PPTABLE].version = 0x01; 230 priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t); 231 priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE; 232 233 /* allocate space for watermarks table */ 234 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev, 235 sizeof(Watermarks_t), 236 PAGE_SIZE, 237 AMDGPU_GEM_DOMAIN_VRAM, 238 &priv->smu_tables.entry[WMTABLE].handle, 239 &priv->smu_tables.entry[WMTABLE].mc_addr, 240 &priv->smu_tables.entry[WMTABLE].table); 241 242 if (ret) 243 goto err0; 244 245 priv->smu_tables.entry[WMTABLE].version = 0x01; 246 priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t); 247 priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS; 248 249 /* allocate space for AVFS table */ 250 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev, 251 sizeof(AvfsTable_t), 252 PAGE_SIZE, 253 AMDGPU_GEM_DOMAIN_VRAM, 254 &priv->smu_tables.entry[AVFSTABLE].handle, 255 &priv->smu_tables.entry[AVFSTABLE].mc_addr, 256 &priv->smu_tables.entry[AVFSTABLE].table); 257 258 if (ret) 259 goto err1; 260 261 priv->smu_tables.entry[AVFSTABLE].version = 0x01; 262 priv->smu_tables.entry[AVFSTABLE].size = sizeof(AvfsTable_t); 263 priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS; 264 265 tools_size = 0x19000; 266 if (tools_size) { 267 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev, 268 tools_size, 269 PAGE_SIZE, 270 AMDGPU_GEM_DOMAIN_VRAM, 271 &priv->smu_tables.entry[TOOLSTABLE].handle, 272 &priv->smu_tables.entry[TOOLSTABLE].mc_addr, 273 &priv->smu_tables.entry[TOOLSTABLE].table); 274 if (ret) 275 goto err2; 276 priv->smu_tables.entry[TOOLSTABLE].version = 0x01; 277 priv->smu_tables.entry[TOOLSTABLE].size = tools_size; 278 priv->smu_tables.entry[TOOLSTABLE].table_id = TABLE_PMSTATUSLOG; 279 } 280 281 /* allocate space for AVFS Fuse table */ 282 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev, 283 sizeof(AvfsFuseOverride_t), 284 PAGE_SIZE, 285 AMDGPU_GEM_DOMAIN_VRAM, 286 &priv->smu_tables.entry[AVFSFUSETABLE].handle, 287 &priv->smu_tables.entry[AVFSFUSETABLE].mc_addr, 288 &priv->smu_tables.entry[AVFSFUSETABLE].table); 289 if (ret) 290 goto err3; 291 292 priv->smu_tables.entry[AVFSFUSETABLE].version = 0x01; 293 priv->smu_tables.entry[AVFSFUSETABLE].size = sizeof(AvfsFuseOverride_t); 294 priv->smu_tables.entry[AVFSFUSETABLE].table_id = TABLE_AVFS_FUSE_OVERRIDE; 295 296 297 return 0; 298 299 err3: 300 if (priv->smu_tables.entry[TOOLSTABLE].table) 301 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TOOLSTABLE].handle, 302 &priv->smu_tables.entry[TOOLSTABLE].mc_addr, 303 &priv->smu_tables.entry[TOOLSTABLE].table); 304 err2: 305 amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSTABLE].handle, 306 &priv->smu_tables.entry[AVFSTABLE].mc_addr, 307 &priv->smu_tables.entry[AVFSTABLE].table); 308 err1: 309 amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle, 310 &priv->smu_tables.entry[WMTABLE].mc_addr, 311 &priv->smu_tables.entry[WMTABLE].table); 312 err0: 313 amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle, 314 &priv->smu_tables.entry[PPTABLE].mc_addr, 315 &priv->smu_tables.entry[PPTABLE].table); 316 free_backend: 317 kfree(hwmgr->smu_backend); 318 319 return -EINVAL; 320 } 321 322 static int vega10_smu_fini(struct pp_hwmgr *hwmgr) 323 { 324 struct vega10_smumgr *priv = hwmgr->smu_backend; 325 326 if (priv) { 327 amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle, 328 &priv->smu_tables.entry[PPTABLE].mc_addr, 329 &priv->smu_tables.entry[PPTABLE].table); 330 amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle, 331 &priv->smu_tables.entry[WMTABLE].mc_addr, 332 &priv->smu_tables.entry[WMTABLE].table); 333 amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSTABLE].handle, 334 &priv->smu_tables.entry[AVFSTABLE].mc_addr, 335 &priv->smu_tables.entry[AVFSTABLE].table); 336 if (priv->smu_tables.entry[TOOLSTABLE].table) 337 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TOOLSTABLE].handle, 338 &priv->smu_tables.entry[TOOLSTABLE].mc_addr, 339 &priv->smu_tables.entry[TOOLSTABLE].table); 340 amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSFUSETABLE].handle, 341 &priv->smu_tables.entry[AVFSFUSETABLE].mc_addr, 342 &priv->smu_tables.entry[AVFSFUSETABLE].table); 343 kfree(hwmgr->smu_backend); 344 hwmgr->smu_backend = NULL; 345 } 346 return 0; 347 } 348 349 static int vega10_start_smu(struct pp_hwmgr *hwmgr) 350 { 351 if (!smu9_is_smc_ram_running(hwmgr)) 352 return -EINVAL; 353 354 PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr), 355 "Failed to verify SMC interface!", 356 return -EINVAL); 357 358 vega10_set_tools_address(hwmgr); 359 360 return 0; 361 } 362 363 static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, 364 uint16_t table_id, bool rw) 365 { 366 int ret; 367 368 if (rw) 369 ret = vega10_copy_table_from_smc(hwmgr, table, table_id); 370 else 371 ret = vega10_copy_table_to_smc(hwmgr, table, table_id); 372 373 return ret; 374 } 375 376 const struct pp_smumgr_func vega10_smu_funcs = { 377 .name = "vega10_smu", 378 .smu_init = &vega10_smu_init, 379 .smu_fini = &vega10_smu_fini, 380 .start_smu = &vega10_start_smu, 381 .request_smu_load_specific_fw = NULL, 382 .send_msg_to_smc = &smu9_send_msg_to_smc, 383 .send_msg_to_smc_with_parameter = &smu9_send_msg_to_smc_with_parameter, 384 .download_pptable_settings = NULL, 385 .upload_pptable_settings = NULL, 386 .is_dpm_running = vega10_is_dpm_running, 387 .get_argument = smu9_get_argument, 388 .smc_table_manager = vega10_smc_table_manager, 389 }; 390
Indexes created Fri Sep 26 08:10:20 GMT 2025