1 /* $NetBSD: vi_structs.h,v 1.3 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef VI_STRUCTS_H_ 27 #define VI_STRUCTS_H_ 28 29 struct vi_sdma_mqd { 30 uint32_t sdmax_rlcx_rb_cntl; 31 uint32_t sdmax_rlcx_rb_base; 32 uint32_t sdmax_rlcx_rb_base_hi; 33 uint32_t sdmax_rlcx_rb_rptr; 34 uint32_t sdmax_rlcx_rb_wptr; 35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl; 36 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; 37 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; 38 uint32_t sdmax_rlcx_rb_rptr_addr_hi; 39 uint32_t sdmax_rlcx_rb_rptr_addr_lo; 40 uint32_t sdmax_rlcx_ib_cntl; 41 uint32_t sdmax_rlcx_ib_rptr; 42 uint32_t sdmax_rlcx_ib_offset; 43 uint32_t sdmax_rlcx_ib_base_lo; 44 uint32_t sdmax_rlcx_ib_base_hi; 45 uint32_t sdmax_rlcx_ib_size; 46 uint32_t sdmax_rlcx_skip_cntl; 47 uint32_t sdmax_rlcx_context_status; 48 uint32_t sdmax_rlcx_doorbell; 49 uint32_t sdmax_rlcx_virtual_addr; 50 uint32_t sdmax_rlcx_ape1_cntl; 51 uint32_t sdmax_rlcx_doorbell_log; 52 uint32_t reserved_22; 53 uint32_t reserved_23; 54 uint32_t reserved_24; 55 uint32_t reserved_25; 56 uint32_t reserved_26; 57 uint32_t reserved_27; 58 uint32_t reserved_28; 59 uint32_t reserved_29; 60 uint32_t reserved_30; 61 uint32_t reserved_31; 62 uint32_t reserved_32; 63 uint32_t reserved_33; 64 uint32_t reserved_34; 65 uint32_t reserved_35; 66 uint32_t reserved_36; 67 uint32_t reserved_37; 68 uint32_t reserved_38; 69 uint32_t reserved_39; 70 uint32_t reserved_40; 71 uint32_t reserved_41; 72 uint32_t reserved_42; 73 uint32_t reserved_43; 74 uint32_t reserved_44; 75 uint32_t reserved_45; 76 uint32_t reserved_46; 77 uint32_t reserved_47; 78 uint32_t reserved_48; 79 uint32_t reserved_49; 80 uint32_t reserved_50; 81 uint32_t reserved_51; 82 uint32_t reserved_52; 83 uint32_t reserved_53; 84 uint32_t reserved_54; 85 uint32_t reserved_55; 86 uint32_t reserved_56; 87 uint32_t reserved_57; 88 uint32_t reserved_58; 89 uint32_t reserved_59; 90 uint32_t reserved_60; 91 uint32_t reserved_61; 92 uint32_t reserved_62; 93 uint32_t reserved_63; 94 uint32_t reserved_64; 95 uint32_t reserved_65; 96 uint32_t reserved_66; 97 uint32_t reserved_67; 98 uint32_t reserved_68; 99 uint32_t reserved_69; 100 uint32_t reserved_70; 101 uint32_t reserved_71; 102 uint32_t reserved_72; 103 uint32_t reserved_73; 104 uint32_t reserved_74; 105 uint32_t reserved_75; 106 uint32_t reserved_76; 107 uint32_t reserved_77; 108 uint32_t reserved_78; 109 uint32_t reserved_79; 110 uint32_t reserved_80; 111 uint32_t reserved_81; 112 uint32_t reserved_82; 113 uint32_t reserved_83; 114 uint32_t reserved_84; 115 uint32_t reserved_85; 116 uint32_t reserved_86; 117 uint32_t reserved_87; 118 uint32_t reserved_88; 119 uint32_t reserved_89; 120 uint32_t reserved_90; 121 uint32_t reserved_91; 122 uint32_t reserved_92; 123 uint32_t reserved_93; 124 uint32_t reserved_94; 125 uint32_t reserved_95; 126 uint32_t reserved_96; 127 uint32_t reserved_97; 128 uint32_t reserved_98; 129 uint32_t reserved_99; 130 uint32_t reserved_100; 131 uint32_t reserved_101; 132 uint32_t reserved_102; 133 uint32_t reserved_103; 134 uint32_t reserved_104; 135 uint32_t reserved_105; 136 uint32_t reserved_106; 137 uint32_t reserved_107; 138 uint32_t reserved_108; 139 uint32_t reserved_109; 140 uint32_t reserved_110; 141 uint32_t reserved_111; 142 uint32_t reserved_112; 143 uint32_t reserved_113; 144 uint32_t reserved_114; 145 uint32_t reserved_115; 146 uint32_t reserved_116; 147 uint32_t reserved_117; 148 uint32_t reserved_118; 149 uint32_t reserved_119; 150 uint32_t reserved_120; 151 uint32_t reserved_121; 152 uint32_t reserved_122; 153 uint32_t reserved_123; 154 uint32_t reserved_124; 155 uint32_t reserved_125; 156 /* reserved_126,127: repurposed for driver-internal use */ 157 uint32_t sdma_engine_id; 158 uint32_t sdma_queue_id; 159 }; 160 161 struct vi_mqd { 162 uint32_t header; 163 uint32_t compute_dispatch_initiator; 164 uint32_t compute_dim_x; 165 uint32_t compute_dim_y; 166 uint32_t compute_dim_z; 167 uint32_t compute_start_x; 168 uint32_t compute_start_y; 169 uint32_t compute_start_z; 170 uint32_t compute_num_thread_x; 171 uint32_t compute_num_thread_y; 172 uint32_t compute_num_thread_z; 173 uint32_t compute_pipelinestat_enable; 174 uint32_t compute_perfcount_enable; 175 uint32_t compute_pgm_lo; 176 uint32_t compute_pgm_hi; 177 uint32_t compute_tba_lo; 178 uint32_t compute_tba_hi; 179 uint32_t compute_tma_lo; 180 uint32_t compute_tma_hi; 181 uint32_t compute_pgm_rsrc1; 182 uint32_t compute_pgm_rsrc2; 183 uint32_t compute_vmid; 184 uint32_t compute_resource_limits; 185 uint32_t compute_static_thread_mgmt_se0; 186 uint32_t compute_static_thread_mgmt_se1; 187 uint32_t compute_tmpring_size; 188 uint32_t compute_static_thread_mgmt_se2; 189 uint32_t compute_static_thread_mgmt_se3; 190 uint32_t compute_restart_x; 191 uint32_t compute_restart_y; 192 uint32_t compute_restart_z; 193 uint32_t compute_thread_trace_enable; 194 uint32_t compute_misc_reserved; 195 uint32_t compute_dispatch_id; 196 uint32_t compute_threadgroup_id; 197 uint32_t compute_relaunch; 198 uint32_t compute_wave_restore_addr_lo; 199 uint32_t compute_wave_restore_addr_hi; 200 uint32_t compute_wave_restore_control; 201 uint32_t reserved9; 202 uint32_t reserved10; 203 uint32_t reserved11; 204 uint32_t reserved12; 205 uint32_t reserved13; 206 uint32_t reserved14; 207 uint32_t reserved15; 208 uint32_t reserved16; 209 uint32_t reserved17; 210 uint32_t reserved18; 211 uint32_t reserved19; 212 uint32_t reserved20; 213 uint32_t reserved21; 214 uint32_t reserved22; 215 uint32_t reserved23; 216 uint32_t reserved24; 217 uint32_t reserved25; 218 uint32_t reserved26; 219 uint32_t reserved27; 220 uint32_t reserved28; 221 uint32_t reserved29; 222 uint32_t reserved30; 223 uint32_t reserved31; 224 uint32_t reserved32; 225 uint32_t reserved33; 226 uint32_t reserved34; 227 uint32_t compute_user_data_0; 228 uint32_t compute_user_data_1; 229 uint32_t compute_user_data_2; 230 uint32_t compute_user_data_3; 231 uint32_t compute_user_data_4; 232 uint32_t compute_user_data_5; 233 uint32_t compute_user_data_6; 234 uint32_t compute_user_data_7; 235 uint32_t compute_user_data_8; 236 uint32_t compute_user_data_9; 237 uint32_t compute_user_data_10; 238 uint32_t compute_user_data_11; 239 uint32_t compute_user_data_12; 240 uint32_t compute_user_data_13; 241 uint32_t compute_user_data_14; 242 uint32_t compute_user_data_15; 243 uint32_t cp_compute_csinvoc_count_lo; 244 uint32_t cp_compute_csinvoc_count_hi; 245 uint32_t reserved35; 246 uint32_t reserved36; 247 uint32_t reserved37; 248 uint32_t cp_mqd_query_time_lo; 249 uint32_t cp_mqd_query_time_hi; 250 uint32_t cp_mqd_connect_start_time_lo; 251 uint32_t cp_mqd_connect_start_time_hi; 252 uint32_t cp_mqd_connect_end_time_lo; 253 uint32_t cp_mqd_connect_end_time_hi; 254 uint32_t cp_mqd_connect_end_wf_count; 255 uint32_t cp_mqd_connect_end_pq_rptr; 256 uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr; 257 uint32_t cp_mqd_connect_end_ib_rptr; 258 uint32_t reserved38; 259 uint32_t reserved39; 260 uint32_t cp_mqd_save_start_time_lo; 261 uint32_t cp_mqd_save_start_time_hi; 262 uint32_t cp_mqd_save_end_time_lo; 263 uint32_t cp_mqd_save_end_time_hi; 264 uint32_t cp_mqd_restore_start_time_lo; 265 uint32_t cp_mqd_restore_start_time_hi; 266 uint32_t cp_mqd_restore_end_time_lo; 267 uint32_t cp_mqd_restore_end_time_hi; 268 uint32_t disable_queue; 269 uint32_t reserved41; 270 uint32_t gds_cs_ctxsw_cnt0; 271 uint32_t gds_cs_ctxsw_cnt1; 272 uint32_t gds_cs_ctxsw_cnt2; 273 uint32_t gds_cs_ctxsw_cnt3; 274 uint32_t reserved42; 275 uint32_t reserved43; 276 uint32_t cp_pq_exe_status_lo; 277 uint32_t cp_pq_exe_status_hi; 278 uint32_t cp_packet_id_lo; 279 uint32_t cp_packet_id_hi; 280 uint32_t cp_packet_exe_status_lo; 281 uint32_t cp_packet_exe_status_hi; 282 uint32_t gds_save_base_addr_lo; 283 uint32_t gds_save_base_addr_hi; 284 uint32_t gds_save_mask_lo; 285 uint32_t gds_save_mask_hi; 286 uint32_t ctx_save_base_addr_lo; 287 uint32_t ctx_save_base_addr_hi; 288 uint32_t dynamic_cu_mask_addr_lo; 289 uint32_t dynamic_cu_mask_addr_hi; 290 uint32_t cp_mqd_base_addr_lo; 291 uint32_t cp_mqd_base_addr_hi; 292 uint32_t cp_hqd_active; 293 uint32_t cp_hqd_vmid; 294 uint32_t cp_hqd_persistent_state; 295 uint32_t cp_hqd_pipe_priority; 296 uint32_t cp_hqd_queue_priority; 297 uint32_t cp_hqd_quantum; 298 uint32_t cp_hqd_pq_base_lo; 299 uint32_t cp_hqd_pq_base_hi; 300 uint32_t cp_hqd_pq_rptr; 301 uint32_t cp_hqd_pq_rptr_report_addr_lo; 302 uint32_t cp_hqd_pq_rptr_report_addr_hi; 303 uint32_t cp_hqd_pq_wptr_poll_addr_lo; 304 uint32_t cp_hqd_pq_wptr_poll_addr_hi; 305 uint32_t cp_hqd_pq_doorbell_control; 306 uint32_t cp_hqd_pq_wptr; 307 uint32_t cp_hqd_pq_control; 308 uint32_t cp_hqd_ib_base_addr_lo; 309 uint32_t cp_hqd_ib_base_addr_hi; 310 uint32_t cp_hqd_ib_rptr; 311 uint32_t cp_hqd_ib_control; 312 uint32_t cp_hqd_iq_timer; 313 uint32_t cp_hqd_iq_rptr; 314 uint32_t cp_hqd_dequeue_request; 315 uint32_t cp_hqd_dma_offload; 316 uint32_t cp_hqd_sema_cmd; 317 uint32_t cp_hqd_msg_type; 318 uint32_t cp_hqd_atomic0_preop_lo; 319 uint32_t cp_hqd_atomic0_preop_hi; 320 uint32_t cp_hqd_atomic1_preop_lo; 321 uint32_t cp_hqd_atomic1_preop_hi; 322 uint32_t cp_hqd_hq_status0; 323 uint32_t cp_hqd_hq_control0; 324 uint32_t cp_mqd_control; 325 uint32_t cp_hqd_hq_status1; 326 uint32_t cp_hqd_hq_control1; 327 uint32_t cp_hqd_eop_base_addr_lo; 328 uint32_t cp_hqd_eop_base_addr_hi; 329 uint32_t cp_hqd_eop_control; 330 uint32_t cp_hqd_eop_rptr; 331 uint32_t cp_hqd_eop_wptr; 332 uint32_t cp_hqd_eop_done_events; 333 uint32_t cp_hqd_ctx_save_base_addr_lo; 334 uint32_t cp_hqd_ctx_save_base_addr_hi; 335 uint32_t cp_hqd_ctx_save_control; 336 uint32_t cp_hqd_cntl_stack_offset; 337 uint32_t cp_hqd_cntl_stack_size; 338 uint32_t cp_hqd_wg_state_offset; 339 uint32_t cp_hqd_ctx_save_size; 340 uint32_t cp_hqd_gds_resource_state; 341 uint32_t cp_hqd_error; 342 uint32_t cp_hqd_eop_wptr_mem; 343 uint32_t cp_hqd_eop_dones; 344 uint32_t reserved46; 345 uint32_t reserved47; 346 uint32_t reserved48; 347 uint32_t reserved49; 348 uint32_t reserved50; 349 uint32_t reserved51; 350 uint32_t reserved52; 351 uint32_t reserved53; 352 uint32_t reserved54; 353 uint32_t reserved55; 354 uint32_t iqtimer_pkt_header; 355 uint32_t iqtimer_pkt_dw0; 356 uint32_t iqtimer_pkt_dw1; 357 uint32_t iqtimer_pkt_dw2; 358 uint32_t iqtimer_pkt_dw3; 359 uint32_t iqtimer_pkt_dw4; 360 uint32_t iqtimer_pkt_dw5; 361 uint32_t iqtimer_pkt_dw6; 362 uint32_t iqtimer_pkt_dw7; 363 uint32_t iqtimer_pkt_dw8; 364 uint32_t iqtimer_pkt_dw9; 365 uint32_t iqtimer_pkt_dw10; 366 uint32_t iqtimer_pkt_dw11; 367 uint32_t iqtimer_pkt_dw12; 368 uint32_t iqtimer_pkt_dw13; 369 uint32_t iqtimer_pkt_dw14; 370 uint32_t iqtimer_pkt_dw15; 371 uint32_t iqtimer_pkt_dw16; 372 uint32_t iqtimer_pkt_dw17; 373 uint32_t iqtimer_pkt_dw18; 374 uint32_t iqtimer_pkt_dw19; 375 uint32_t iqtimer_pkt_dw20; 376 uint32_t iqtimer_pkt_dw21; 377 uint32_t iqtimer_pkt_dw22; 378 uint32_t iqtimer_pkt_dw23; 379 uint32_t iqtimer_pkt_dw24; 380 uint32_t iqtimer_pkt_dw25; 381 uint32_t iqtimer_pkt_dw26; 382 uint32_t iqtimer_pkt_dw27; 383 uint32_t iqtimer_pkt_dw28; 384 uint32_t iqtimer_pkt_dw29; 385 uint32_t iqtimer_pkt_dw30; 386 uint32_t iqtimer_pkt_dw31; 387 uint32_t reserved56; 388 uint32_t reserved57; 389 uint32_t reserved58; 390 uint32_t set_resources_header; 391 uint32_t set_resources_dw1; 392 uint32_t set_resources_dw2; 393 uint32_t set_resources_dw3; 394 uint32_t set_resources_dw4; 395 uint32_t set_resources_dw5; 396 uint32_t set_resources_dw6; 397 uint32_t set_resources_dw7; 398 uint32_t reserved59; 399 uint32_t reserved60; 400 uint32_t reserved61; 401 uint32_t reserved62; 402 uint32_t reserved63; 403 uint32_t reserved64; 404 uint32_t reserved65; 405 uint32_t reserved66; 406 uint32_t reserved67; 407 uint32_t reserved68; 408 uint32_t reserved69; 409 uint32_t reserved70; 410 uint32_t reserved71; 411 uint32_t reserved72; 412 uint32_t reserved73; 413 uint32_t reserved74; 414 uint32_t reserved75; 415 uint32_t reserved76; 416 uint32_t reserved77; 417 uint32_t reserved78; 418 uint32_t reserved_t[256]; 419 }; 420 421 struct vi_mqd_allocation { 422 struct vi_mqd mqd; 423 uint32_t wptr_poll_mem; 424 uint32_t rptr_report_mem; 425 uint32_t dynamic_cu_mask; 426 uint32_t dynamic_rb_mask; 427 }; 428 429 struct vi_ce_ib_state { 430 uint32_t ce_ib_completion_status; 431 uint32_t ce_constegnine_count; 432 uint32_t ce_ibOffset_ib1; 433 uint32_t ce_ibOffset_ib2; 434 }; /* Total of 4 DWORD */ 435 436 struct vi_de_ib_state { 437 uint32_t ib_completion_status; 438 uint32_t de_constEngine_count; 439 uint32_t ib_offset_ib1; 440 uint32_t ib_offset_ib2; 441 uint32_t preamble_begin_ib1; 442 uint32_t preamble_begin_ib2; 443 uint32_t preamble_end_ib1; 444 uint32_t preamble_end_ib2; 445 uint32_t draw_indirect_baseLo; 446 uint32_t draw_indirect_baseHi; 447 uint32_t disp_indirect_baseLo; 448 uint32_t disp_indirect_baseHi; 449 uint32_t gds_backup_addrlo; 450 uint32_t gds_backup_addrhi; 451 uint32_t index_base_addrlo; 452 uint32_t index_base_addrhi; 453 uint32_t sample_cntl; 454 }; /* Total of 17 DWORD */ 455 456 struct vi_ce_ib_state_chained_ib { 457 /* section of non chained ib part */ 458 uint32_t ce_ib_completion_status; 459 uint32_t ce_constegnine_count; 460 uint32_t ce_ibOffset_ib1; 461 uint32_t ce_ibOffset_ib2; 462 463 /* section of chained ib */ 464 uint32_t ce_chainib_addrlo_ib1; 465 uint32_t ce_chainib_addrlo_ib2; 466 uint32_t ce_chainib_addrhi_ib1; 467 uint32_t ce_chainib_addrhi_ib2; 468 uint32_t ce_chainib_size_ib1; 469 uint32_t ce_chainib_size_ib2; 470 }; /* total 10 DWORD */ 471 472 struct vi_de_ib_state_chained_ib { 473 /* section of non chained ib part */ 474 uint32_t ib_completion_status; 475 uint32_t de_constEngine_count; 476 uint32_t ib_offset_ib1; 477 uint32_t ib_offset_ib2; 478 479 /* section of chained ib */ 480 uint32_t chain_ib_addrlo_ib1; 481 uint32_t chain_ib_addrlo_ib2; 482 uint32_t chain_ib_addrhi_ib1; 483 uint32_t chain_ib_addrhi_ib2; 484 uint32_t chain_ib_size_ib1; 485 uint32_t chain_ib_size_ib2; 486 487 /* section of non chained ib part */ 488 uint32_t preamble_begin_ib1; 489 uint32_t preamble_begin_ib2; 490 uint32_t preamble_end_ib1; 491 uint32_t preamble_end_ib2; 492 493 /* section of chained ib */ 494 uint32_t chain_ib_pream_addrlo_ib1; 495 uint32_t chain_ib_pream_addrlo_ib2; 496 uint32_t chain_ib_pream_addrhi_ib1; 497 uint32_t chain_ib_pream_addrhi_ib2; 498 499 /* section of non chained ib part */ 500 uint32_t draw_indirect_baseLo; 501 uint32_t draw_indirect_baseHi; 502 uint32_t disp_indirect_baseLo; 503 uint32_t disp_indirect_baseHi; 504 uint32_t gds_backup_addrlo; 505 uint32_t gds_backup_addrhi; 506 uint32_t index_base_addrlo; 507 uint32_t index_base_addrhi; 508 uint32_t sample_cntl; 509 }; /* Total of 27 DWORD */ 510 511 struct vi_gfx_meta_data { 512 /* 4 DWORD, address must be 4KB aligned */ 513 struct vi_ce_ib_state ce_payload; 514 uint32_t reserved1[60]; 515 /* 17 DWORD, address must be 64B aligned */ 516 struct vi_de_ib_state de_payload; 517 /* PFP IB base address which get pre-empted */ 518 uint32_t DeIbBaseAddrLo; 519 uint32_t DeIbBaseAddrHi; 520 uint32_t reserved2[941]; 521 }; /* Total of 4K Bytes */ 522 523 struct vi_gfx_meta_data_chained_ib { 524 /* 10 DWORD, address must be 4KB aligned */ 525 struct vi_ce_ib_state_chained_ib ce_payload; 526 uint32_t reserved1[54]; 527 /* 27 DWORD, address must be 64B aligned */ 528 struct vi_de_ib_state_chained_ib de_payload; 529 /* PFP IB base address which get pre-empted */ 530 uint32_t DeIbBaseAddrLo; 531 uint32_t DeIbBaseAddrHi; 532 uint32_t reserved2[931]; 533 }; /* Total of 4K Bytes */ 534 535 #endif /* VI_STRUCTS_H_ */ 536
Indexes created Sat Sep 20 22:09:52 GMT 2025