1 /* $NetBSD: via82c586.c,v 1.12 2011/07/01 17:37:27 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1999, by UCHIYAMA Yasushi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. The name of the developer may NOT be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 /* 59 * Support for the VIA 82c586 PCI-ISA bridge interrupt controller. 60 */ 61 62 #include <sys/cdefs.h> 63 __KERNEL_RCSID(0, "$NetBSD: via82c586.c,v 1.12 2011/07/01 17:37:27 dyoung Exp $"); 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/device.h> 68 69 #include <machine/intr.h> 70 #include <sys/bus.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <i386/pci/pci_intr_fixup.h> 77 #include <i386/pci/via82c586reg.h> 78 #include <i386/pci/piixvar.h> 79 80 int via82c586_getclink(pciintr_icu_handle_t, int, int *); 81 int via82c586_get_intr(pciintr_icu_handle_t, int, int *); 82 int via82c586_set_intr(pciintr_icu_handle_t, int, int); 83 int via82c586_get_trigger(pciintr_icu_handle_t, int, int *); 84 int via82c586_set_trigger(pciintr_icu_handle_t, int, int); 85 86 const struct pciintr_icu via82c586_pci_icu = { 87 via82c586_getclink, 88 via82c586_get_intr, 89 via82c586_set_intr, 90 via82c586_get_trigger, 91 via82c586_set_trigger, 92 }; 93 94 const int vp3_cfg_trigger_shift[] = { 95 VP3_CFG_TRIGGER_SHIFT_PIRQA, 96 VP3_CFG_TRIGGER_SHIFT_PIRQB, 97 VP3_CFG_TRIGGER_SHIFT_PIRQC, 98 VP3_CFG_TRIGGER_SHIFT_PIRQD, 99 }; 100 101 #define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \ 102 VP3_CFG_TRIGGER_MASK) 103 104 const int vp3_cfg_intr_shift[] = { 105 VP3_CFG_INTR_SHIFT_PIRQA, 106 VP3_CFG_INTR_SHIFT_PIRQB, 107 VP3_CFG_INTR_SHIFT_PIRQC, 108 VP3_CFG_INTR_SHIFT_PIRQD, 109 VP3_CFG_INTR_SHIFT_PIRQ0, 110 VP3_CFG_INTR_SHIFT_PIRQ1, 111 VP3_CFG_INTR_SHIFT_PIRQ2, 112 }; 113 114 #define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \ 115 VP3_CFG_INTR_MASK) 116 117 int 118 via82c586_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 119 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 120 { 121 pcireg_t reg; 122 123 if (piix_init(pc, iot, tag, ptagp, phandp) == 0) { 124 *ptagp = &via82c586_pci_icu; 125 126 /* 127 * Enable EISA ELCR. 128 */ 129 reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG); 130 reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE << 131 VP3_CFG_MISCCTRL2_SHIFT; 132 pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg); 133 134 return (0); 135 } 136 137 return (1); 138 } 139 140 int 141 via82c586_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 142 { 143 144 if (VP3_LEGAL_LINK(link - 1)) { 145 *clinkp = link - 1; 146 return (0); 147 } 148 149 return (1); 150 } 151 152 int 153 via82c586_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 154 { 155 struct piix_handle *ph = v; 156 pcireg_t reg; 157 int val; 158 159 if (VP3_LEGAL_LINK(clink) == 0) 160 return (1); 161 162 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 163 val = VP3_PIRQ(reg, clink); 164 *irqp = (val == VP3_PIRQ_NONE) ? 165 X86_PCI_INTERRUPT_LINE_NO_CONNECTION : val; 166 167 return (0); 168 } 169 170 int 171 via82c586_set_intr(pciintr_icu_handle_t v, int clink, int irq) 172 { 173 struct piix_handle *ph = v; 174 int shift, val; 175 pcireg_t reg; 176 177 if (VP3_LEGAL_LINK(clink) == 0 || VP3_LEGAL_IRQ(irq) == 0) 178 return (1); 179 180 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG); 181 via82c586_get_intr(v, clink, &val); 182 shift = vp3_cfg_intr_shift[clink]; 183 reg &= ~(VP3_CFG_INTR_MASK << shift); 184 reg |= (irq << shift); 185 pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg); 186 if (via82c586_get_intr(v, clink, &val) != 0 || 187 val != irq) 188 return (1); 189 190 return (0); 191 } 192 193 int 194 via82c586_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 195 { 196 struct piix_handle *ph = v; 197 int i, error, check_consistency, pciirq, pcitrigger = IST_NONE; 198 pcireg_t reg; 199 200 if (VP3_LEGAL_IRQ(irq) == 0) 201 return (1); 202 203 check_consistency = 0; 204 for (i = 0; i <= 3; i++) { 205 via82c586_get_intr(v, i, &pciirq); 206 if (pciirq == irq) { 207 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 208 VP3_CFG_PIRQ_REG); 209 if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE) 210 pcitrigger = IST_EDGE; 211 else 212 pcitrigger = IST_LEVEL; 213 check_consistency = 1; 214 break; 215 } 216 } 217 218 error = piix_get_trigger(v, irq, triggerp); 219 if (error == 0 && check_consistency && pcitrigger != *triggerp) 220 return (1); 221 return (error); 222 } 223 224 int 225 via82c586_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 226 { 227 struct piix_handle *ph = v; 228 int i, pciirq, shift, testtrig; 229 pcireg_t reg; 230 231 if (VP3_LEGAL_IRQ(irq) == 0) 232 return (1); 233 234 for (i = 0; i <= 3; i++) { 235 via82c586_get_intr(v, i, &pciirq); 236 if (pciirq == irq) { 237 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, 238 VP3_CFG_PIRQ_REG); 239 shift = vp3_cfg_trigger_shift[i]; 240 if (trigger == IST_LEVEL) 241 reg &= ~(VP3_CFG_TRIGGER_MASK << shift); 242 else 243 reg |= (VP3_CFG_TRIGGER_EDGE << shift); 244 pci_conf_write(ph->ph_pc, ph->ph_tag, 245 VP3_CFG_PIRQ_REG, reg); 246 break; 247 } 248 } 249 250 if (piix_set_trigger(v, irq, trigger) != 0 || 251 via82c586_get_trigger(v, irq, &testtrig) != 0 || 252 testtrig != trigger) 253 return (1); 254 255 return (0); 256 } 257
Indexes created Tue Sep 23 02:09:52 GMT 2025