1 /* $NetBSD: vlv_dsi_pll.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Shobhit Kumar <shobhit.kumar (at) intel.com> 27 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu (at) intel.com> 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vlv_dsi_pll.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $"); 32 33 #include <linux/kernel.h> 34 35 #include "i915_drv.h" 36 #include "intel_display_types.h" 37 #include "intel_dsi.h" 38 #include "intel_sideband.h" 39 40 static const u16 lfsr_converts[] = { 41 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 42 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 43 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 44 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 45 }; 46 47 /* Get DSI clock from pixel clock */ 48 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, 49 int lane_count) 50 { 51 u32 dsi_clk_khz; 52 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); 53 54 /* DSI data rate = pixel clock * bits per pixel / lane count 55 pixel clock is converted from KHz to Hz */ 56 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 57 58 return dsi_clk_khz; 59 } 60 61 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 62 struct intel_crtc_state *config, 63 int target_dsi_clk) 64 { 65 unsigned int m_min, m_max, p_min = 2, p_max = 6; 66 unsigned int m, n, p; 67 unsigned int calc_m, calc_p; 68 int delta, ref_clk; 69 70 /* target_dsi_clk is expected in kHz */ 71 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 72 DRM_ERROR("DSI CLK Out of Range\n"); 73 return -ECHRNG; 74 } 75 76 if (IS_CHERRYVIEW(dev_priv)) { 77 ref_clk = 100000; 78 n = 4; 79 m_min = 70; 80 m_max = 96; 81 } else { 82 ref_clk = 25000; 83 n = 1; 84 m_min = 62; 85 m_max = 92; 86 } 87 88 calc_p = p_min; 89 calc_m = m_min; 90 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); 91 92 for (m = m_min; m <= m_max && delta; m++) { 93 for (p = p_min; p <= p_max && delta; p++) { 94 /* 95 * Find the optimal m and p divisors with minimal delta 96 * +/- the required clock 97 */ 98 int calc_dsi_clk = (m * ref_clk) / (p * n); 99 int d = abs(target_dsi_clk - calc_dsi_clk); 100 if (d < delta) { 101 delta = d; 102 calc_m = m; 103 calc_p = p; 104 } 105 } 106 } 107 108 /* register has log2(N1), this works fine for powers of two */ 109 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 110 config->dsi_pll.div = 111 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT | 112 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT; 113 114 return 0; 115 } 116 117 /* 118 * XXX: The muxing and gating is hard coded for now. Need to add support for 119 * sharing PLLs with two DSI outputs. 120 */ 121 int vlv_dsi_pll_compute(struct intel_encoder *encoder, 122 struct intel_crtc_state *config) 123 { 124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 125 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 126 int ret; 127 u32 dsi_clk; 128 129 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 130 intel_dsi->lane_count); 131 132 ret = dsi_calc_mnp(dev_priv, config, dsi_clk); 133 if (ret) { 134 DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); 135 return ret; 136 } 137 138 if (intel_dsi->ports & (1 << PORT_A)) 139 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 140 141 if (intel_dsi->ports & (1 << PORT_C)) 142 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 143 144 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; 145 146 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", 147 config->dsi_pll.div, config->dsi_pll.ctrl); 148 149 return 0; 150 } 151 152 void vlv_dsi_pll_enable(struct intel_encoder *encoder, 153 const struct intel_crtc_state *config) 154 { 155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 156 157 DRM_DEBUG_KMS("\n"); 158 159 vlv_cck_get(dev_priv); 160 161 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 162 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); 163 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 164 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); 165 166 /* wait at least 0.5 us after ungating before enabling VCO, 167 * allow hrtimer subsystem optimization by relaxing timing 168 */ 169 usleep_range(10, 50); 170 171 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); 172 173 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 174 DSI_PLL_LOCK, 20)) { 175 176 vlv_cck_put(dev_priv); 177 DRM_ERROR("DSI PLL lock failed\n"); 178 return; 179 } 180 vlv_cck_put(dev_priv); 181 182 DRM_DEBUG_KMS("DSI PLL locked\n"); 183 } 184 185 void vlv_dsi_pll_disable(struct intel_encoder *encoder) 186 { 187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 188 u32 tmp; 189 190 DRM_DEBUG_KMS("\n"); 191 192 vlv_cck_get(dev_priv); 193 194 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 195 tmp &= ~DSI_PLL_VCO_EN; 196 tmp |= DSI_PLL_LDO_GATE; 197 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 198 199 vlv_cck_put(dev_priv); 200 } 201 202 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 203 { 204 bool enabled; 205 u32 val; 206 u32 mask; 207 208 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; 209 val = I915_READ(BXT_DSI_PLL_ENABLE); 210 enabled = (val & mask) == mask; 211 212 if (!enabled) 213 return false; 214 215 /* 216 * Dividers must be programmed with valid values. As per BSEPC, for 217 * GEMINLAKE only PORT A divider values are checked while for BXT 218 * both divider values are validated. Check this here for 219 * paranoia, since BIOS is known to misconfigure PLLs in this way at 220 * times, and since accessing DSI registers with invalid dividers 221 * causes a system hang. 222 */ 223 val = I915_READ(BXT_DSI_PLL_CTL); 224 if (IS_GEMINILAKE(dev_priv)) { 225 if (!(val & BXT_DSIA_16X_MASK)) { 226 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val); 227 enabled = false; 228 } 229 } else { 230 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { 231 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val); 232 enabled = false; 233 } 234 } 235 236 return enabled; 237 } 238 239 void bxt_dsi_pll_disable(struct intel_encoder *encoder) 240 { 241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 242 u32 val; 243 244 DRM_DEBUG_KMS("\n"); 245 246 val = I915_READ(BXT_DSI_PLL_ENABLE); 247 val &= ~BXT_DSI_PLL_DO_ENABLE; 248 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 249 250 /* 251 * PLL lock should deassert within 200us. 252 * Wait up to 1ms before timing out. 253 */ 254 if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE, 255 BXT_DSI_PLL_LOCKED, 1)) 256 DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); 257 } 258 259 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, 260 struct intel_crtc_state *config) 261 { 262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 263 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 264 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 265 u32 dsi_clock, pclk; 266 u32 pll_ctl, pll_div; 267 u32 m = 0, p = 0, n; 268 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; 269 int i; 270 271 DRM_DEBUG_KMS("\n"); 272 273 vlv_cck_get(dev_priv); 274 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 275 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 276 vlv_cck_put(dev_priv); 277 278 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; 279 config->dsi_pll.div = pll_div; 280 281 /* mask out other bits and extract the P1 divisor */ 282 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 283 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 284 285 /* N1 divisor */ 286 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 287 n = 1 << n; /* register has log2(N1) */ 288 289 /* mask out the other bits and extract the M1 divisor */ 290 pll_div &= DSI_PLL_M1_DIV_MASK; 291 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 292 293 while (pll_ctl) { 294 pll_ctl = pll_ctl >> 1; 295 p++; 296 } 297 p--; 298 299 if (!p) { 300 DRM_ERROR("wrong P1 divisor\n"); 301 return 0; 302 } 303 304 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 305 if (lfsr_converts[i] == pll_div) 306 break; 307 } 308 309 if (i == ARRAY_SIZE(lfsr_converts)) { 310 DRM_ERROR("wrong m_seed programmed\n"); 311 return 0; 312 } 313 314 m = i + 62; 315 316 dsi_clock = (m * refclk) / (p * n); 317 318 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); 319 320 return pclk; 321 } 322 323 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, 324 struct intel_crtc_state *config) 325 { 326 u32 pclk; 327 u32 dsi_clk; 328 u32 dsi_ratio; 329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 330 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 331 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 332 333 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); 334 335 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 336 337 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; 338 339 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); 340 341 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); 342 return pclk; 343 } 344 345 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 346 { 347 u32 temp; 348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 349 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 350 351 temp = I915_READ(MIPI_CTRL(port)); 352 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 353 I915_WRITE(MIPI_CTRL(port), temp | 354 intel_dsi->escape_clk_div << 355 ESCAPE_CLOCK_DIVIDER_SHIFT); 356 } 357 358 static void glk_dsi_program_esc_clock(struct drm_device *dev, 359 const struct intel_crtc_state *config) 360 { 361 struct drm_i915_private *dev_priv = to_i915(dev); 362 u32 dsi_rate = 0; 363 u32 pll_ratio = 0; 364 u32 ddr_clk = 0; 365 u32 div1_value = 0; 366 u32 div2_value = 0; 367 u32 txesc1_div = 0; 368 u32 txesc2_div = 0; 369 370 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 371 372 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 373 374 ddr_clk = dsi_rate / 2; 375 376 /* Variable divider value */ 377 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000); 378 379 /* Calculate TXESC1 divider */ 380 if (div1_value <= 10) 381 txesc1_div = div1_value; 382 else if ((div1_value > 10) && (div1_value <= 20)) 383 txesc1_div = DIV_ROUND_UP(div1_value, 2); 384 else if ((div1_value > 20) && (div1_value <= 30)) 385 txesc1_div = DIV_ROUND_UP(div1_value, 4); 386 else if ((div1_value > 30) && (div1_value <= 40)) 387 txesc1_div = DIV_ROUND_UP(div1_value, 6); 388 else if ((div1_value > 40) && (div1_value <= 50)) 389 txesc1_div = DIV_ROUND_UP(div1_value, 8); 390 else 391 txesc1_div = 10; 392 393 /* Calculate TXESC2 divider */ 394 div2_value = DIV_ROUND_UP(div1_value, txesc1_div); 395 396 if (div2_value < 10) 397 txesc2_div = div2_value; 398 else 399 txesc2_div = 10; 400 401 I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); 402 I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); 403 } 404 405 /* Program BXT Mipi clocks and dividers */ 406 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 407 const struct intel_crtc_state *config) 408 { 409 struct drm_i915_private *dev_priv = to_i915(dev); 410 u32 tmp; 411 u32 dsi_rate = 0; 412 u32 pll_ratio = 0; 413 u32 rx_div; 414 u32 tx_div; 415 u32 rx_div_upper; 416 u32 rx_div_lower; 417 u32 mipi_8by3_divider; 418 419 /* Clear old configurations */ 420 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); 421 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 422 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 423 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 424 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 425 426 /* Get the current DSI rate(actual) */ 427 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 428 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 429 430 /* 431 * tx clock should be <= 20MHz and the div value must be 432 * subtracted by 1 as per bspec 433 */ 434 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; 435 /* 436 * rx clock should be <= 150MHz and the div value must be 437 * subtracted by 1 as per bspec 438 */ 439 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; 440 441 /* 442 * rx divider value needs to be updated in the 443 * two differnt bit fields in the register hence splitting the 444 * rx divider value accordingly 445 */ 446 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; 447 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; 448 449 mipi_8by3_divider = 0x2; 450 451 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); 452 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); 453 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); 454 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); 455 456 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); 457 } 458 459 int bxt_dsi_pll_compute(struct intel_encoder *encoder, 460 struct intel_crtc_state *config) 461 { 462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 463 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 464 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max; 465 u32 dsi_clk; 466 467 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 468 intel_dsi->lane_count); 469 470 /* 471 * From clock diagram, to get PLL ratio divider, divide double of DSI 472 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to 473 * round 'up' the result 474 */ 475 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); 476 477 if (IS_BROXTON(dev_priv)) { 478 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN; 479 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX; 480 } else { 481 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN; 482 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX; 483 } 484 485 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) { 486 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); 487 return -ECHRNG; 488 } else 489 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n"); 490 491 /* 492 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x 493 * Spec says both have to be programmed, even if one is not getting 494 * used. Configure MIPI_CLOCK_CTL dividers in modeset 495 */ 496 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; 497 498 /* As per recommendation from hardware team, 499 * Prog PVD ratio =1 if dsi ratio <= 50 500 */ 501 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50) 502 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; 503 504 return 0; 505 } 506 507 void bxt_dsi_pll_enable(struct intel_encoder *encoder, 508 const struct intel_crtc_state *config) 509 { 510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 511 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 512 enum port port; 513 u32 val; 514 515 DRM_DEBUG_KMS("\n"); 516 517 /* Configure PLL vales */ 518 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); 519 POSTING_READ(BXT_DSI_PLL_CTL); 520 521 /* Program TX, RX, Dphy clocks */ 522 if (IS_BROXTON(dev_priv)) { 523 for_each_dsi_port(port, intel_dsi->ports) 524 bxt_dsi_program_clocks(encoder->base.dev, port, config); 525 } else { 526 glk_dsi_program_esc_clock(encoder->base.dev, config); 527 } 528 529 /* Enable DSI PLL */ 530 val = I915_READ(BXT_DSI_PLL_ENABLE); 531 val |= BXT_DSI_PLL_DO_ENABLE; 532 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 533 534 /* Timeout and fail if PLL not locked */ 535 if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE, 536 BXT_DSI_PLL_LOCKED, 1)) { 537 DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); 538 return; 539 } 540 541 DRM_DEBUG_KMS("DSI PLL locked\n"); 542 } 543 544 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 545 { 546 u32 tmp; 547 struct drm_device *dev = encoder->base.dev; 548 struct drm_i915_private *dev_priv = to_i915(dev); 549 550 /* Clear old configurations */ 551 if (IS_BROXTON(dev_priv)) { 552 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); 553 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 554 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 555 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 556 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 557 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); 558 } else { 559 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); 560 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK; 561 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp); 562 563 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); 564 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK; 565 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp); 566 } 567 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 568 } 569
Indexes created Sat Sep 20 22:09:52 GMT 2025