1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin (at) valinux.com> 28 * Gareth Hughes <gareth (at) valinux.com> 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 #define DRM_AMDGPU_USERQ 0x16 58 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 59 #define DRM_AMDGPU_USERQ_WAIT 0x18 60 61 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 62 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 63 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 64 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 65 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 66 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 67 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 68 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 69 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 70 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 71 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 72 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 73 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 74 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 75 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 76 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 77 #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 78 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 79 #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 80 81 /** 82 * DOC: memory domains 83 * 84 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 85 * Memory in this pool could be swapped out to disk if there is pressure. 86 * 87 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 88 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 89 * pages of system memory, allows GPU access system memory in a linearized 90 * fashion. 91 * 92 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 93 * carved out by the BIOS. 94 * 95 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 96 * across shader threads. 97 * 98 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 99 * execution of all the waves on a device. 100 * 101 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 102 * for appending data. 103 * 104 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 105 * signalling user mode queues. 106 */ 107 #define AMDGPU_GEM_DOMAIN_CPU 0x1 108 #define AMDGPU_GEM_DOMAIN_GTT 0x2 109 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 110 #define AMDGPU_GEM_DOMAIN_GDS 0x8 111 #define AMDGPU_GEM_DOMAIN_GWS 0x10 112 #define AMDGPU_GEM_DOMAIN_OA 0x20 113 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 114 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 115 AMDGPU_GEM_DOMAIN_GTT | \ 116 AMDGPU_GEM_DOMAIN_VRAM | \ 117 AMDGPU_GEM_DOMAIN_GDS | \ 118 AMDGPU_GEM_DOMAIN_GWS | \ 119 AMDGPU_GEM_DOMAIN_OA | \ 120 AMDGPU_GEM_DOMAIN_DOORBELL) 121 122 /* Flag that CPU access will be required for the case of VRAM domain */ 123 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 124 /* Flag that CPU access will not work, this VRAM domain is invisible */ 125 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 126 /* Flag that USWC attributes should be used for GTT */ 127 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 128 /* Flag that the memory should be in VRAM and cleared */ 129 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 130 /* Flag that allocating the BO should use linear VRAM */ 131 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 132 /* Flag that BO is always valid in this VM */ 133 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 134 /* Flag that BO sharing will be explicitly synchronized */ 135 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 136 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 137 * for the second page onward should be set to NC. It should never 138 * be used by user space applications. 139 */ 140 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 141 /* Flag that BO may contain sensitive data that must be wiped before 142 * releasing the memory 143 */ 144 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 145 /* Flag that BO will be encrypted and that the TMZ bit should be 146 * set in the PTEs when mapping this buffer via GPUVM or 147 * accessing it with various hw blocks 148 */ 149 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 150 /* Flag that BO will be used only in preemptible context, which does 151 * not require GTT memory accounting 152 */ 153 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 154 /* Flag that BO can be discarded under memory pressure without keeping the 155 * content. 156 */ 157 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 158 /* Flag that BO is shared coherently between multiple devices or CPU threads. 159 * May depend on GPU instructions to flush caches to system scope explicitly. 160 * 161 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 162 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 163 */ 164 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 165 /* Flag that BO should not be cached by GPU. Coherent without having to flush 166 * GPU caches explicitly 167 * 168 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 169 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 170 */ 171 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 172 /* Flag that BO should be coherent across devices when using device-level 173 * atomics. May depend on GPU instructions to flush caches to device scope 174 * explicitly, promoting them to system scope automatically. 175 * 176 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 177 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 178 */ 179 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 180 181 struct drm_amdgpu_gem_create_in { 182 /** the requested memory size */ 183 __u64 bo_size; 184 /** physical start_addr alignment in bytes for some HW requirements */ 185 __u64 alignment; 186 /** the requested memory domains */ 187 __u64 domains; 188 /** allocation flags */ 189 __u64 domain_flags; 190 }; 191 192 struct drm_amdgpu_gem_create_out { 193 /** returned GEM object handle */ 194 __u32 handle; 195 __u32 _pad; 196 }; 197 198 union drm_amdgpu_gem_create { 199 struct drm_amdgpu_gem_create_in in; 200 struct drm_amdgpu_gem_create_out out; 201 }; 202 203 /** Opcode to create new residency list. */ 204 #define AMDGPU_BO_LIST_OP_CREATE 0 205 /** Opcode to destroy previously created residency list */ 206 #define AMDGPU_BO_LIST_OP_DESTROY 1 207 /** Opcode to update resource information in the list */ 208 #define AMDGPU_BO_LIST_OP_UPDATE 2 209 210 struct drm_amdgpu_bo_list_in { 211 /** Type of operation */ 212 __u32 operation; 213 /** Handle of list or 0 if we want to create one */ 214 __u32 list_handle; 215 /** Number of BOs in list */ 216 __u32 bo_number; 217 /** Size of each element describing BO */ 218 __u32 bo_info_size; 219 /** Pointer to array describing BOs */ 220 __u64 bo_info_ptr; 221 }; 222 223 struct drm_amdgpu_bo_list_entry { 224 /** Handle of BO */ 225 __u32 bo_handle; 226 /** New (if specified) BO priority to be used during migration */ 227 __u32 bo_priority; 228 }; 229 230 struct drm_amdgpu_bo_list_out { 231 /** Handle of resource list */ 232 __u32 list_handle; 233 __u32 _pad; 234 }; 235 236 union drm_amdgpu_bo_list { 237 struct drm_amdgpu_bo_list_in in; 238 struct drm_amdgpu_bo_list_out out; 239 }; 240 241 /* context related */ 242 #define AMDGPU_CTX_OP_ALLOC_CTX 1 243 #define AMDGPU_CTX_OP_FREE_CTX 2 244 #define AMDGPU_CTX_OP_QUERY_STATE 3 245 #define AMDGPU_CTX_OP_QUERY_STATE2 4 246 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 247 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 248 249 /* GPU reset status */ 250 #define AMDGPU_CTX_NO_RESET 0 251 /* this the context caused it */ 252 #define AMDGPU_CTX_GUILTY_RESET 1 253 /* some other context caused it */ 254 #define AMDGPU_CTX_INNOCENT_RESET 2 255 /* unknown cause */ 256 #define AMDGPU_CTX_UNKNOWN_RESET 3 257 258 /* indicate gpu reset occurred after ctx created */ 259 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 260 /* indicate vram lost occurred after ctx created */ 261 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 262 /* indicate some job from this context once cause gpu hang */ 263 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 264 /* indicate some errors are detected by RAS */ 265 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 266 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 267 /* indicate that the reset hasn't completed yet */ 268 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 269 270 /* Context priority level */ 271 #define AMDGPU_CTX_PRIORITY_UNSET -2048 272 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 273 #define AMDGPU_CTX_PRIORITY_LOW -512 274 #define AMDGPU_CTX_PRIORITY_NORMAL 0 275 /* 276 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 277 * CAP_SYS_NICE or DRM_MASTER 278 */ 279 #define AMDGPU_CTX_PRIORITY_HIGH 512 280 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 281 282 /* select a stable profiling pstate for perfmon tools */ 283 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 284 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 285 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 286 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 287 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 288 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 289 290 struct drm_amdgpu_ctx_in { 291 /** AMDGPU_CTX_OP_* */ 292 __u32 op; 293 /** Flags */ 294 __u32 flags; 295 __u32 ctx_id; 296 /** AMDGPU_CTX_PRIORITY_* */ 297 __s32 priority; 298 }; 299 300 union drm_amdgpu_ctx_out { 301 struct { 302 __u32 ctx_id; 303 __u32 _pad; 304 } alloc; 305 306 struct { 307 /** For future use, no flags defined so far */ 308 __u64 flags; 309 /** Number of resets caused by this context so far. */ 310 __u32 hangs; 311 /** Reset status since the last call of the ioctl. */ 312 __u32 reset_status; 313 } state; 314 315 struct { 316 __u32 flags; 317 __u32 _pad; 318 } pstate; 319 }; 320 321 union drm_amdgpu_ctx { 322 struct drm_amdgpu_ctx_in in; 323 union drm_amdgpu_ctx_out out; 324 }; 325 326 /* user queue IOCTL operations */ 327 #define AMDGPU_USERQ_OP_CREATE 1 328 #define AMDGPU_USERQ_OP_FREE 2 329 330 /* queue priority levels */ 331 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3 332 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0 333 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0 334 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1 335 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2 336 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ 337 /* for queues that need access to protected content */ 338 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) 339 340 /* 341 * This structure is a container to pass input configuration 342 * info for all supported userqueue related operations. 343 * For operation AMDGPU_USERQ_OP_CREATE: user is expected 344 * to set all fields, excep the parameter 'queue_id'. 345 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected 346 * to be set is 'queue_id', eveything else is ignored. 347 */ 348 struct drm_amdgpu_userq_in { 349 /** AMDGPU_USERQ_OP_* */ 350 __u32 op; 351 /** Queue id passed for operation USERQ_OP_FREE */ 352 __u32 queue_id; 353 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ 354 __u32 ip_type; 355 /** 356 * @doorbell_handle: the handle of doorbell GEM object 357 * associated to this userqueue client. 358 */ 359 __u32 doorbell_handle; 360 /** 361 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. 362 * Kernel will generate absolute doorbell offset using doorbell_handle 363 * and doorbell_offset in the doorbell bo. 364 */ 365 __u32 doorbell_offset; 366 /** 367 * @flags: flags used for queue parameters 368 */ 369 __u32 flags; 370 371 /** 372 * @queue_va: Virtual address of the GPU memory which holds the queue 373 * object. The queue holds the workload packets. 374 */ 375 __u64 queue_va; 376 /** 377 * @queue_size: Size of the queue in bytes, this needs to be 256-byte 378 * aligned. 379 */ 380 __u64 queue_size; 381 /** 382 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. 383 * This object must be at least 8 byte in size and aligned to 8-byte offset. 384 */ 385 __u64 rptr_va; 386 /** 387 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. 388 * This object must be at least 8 byte in size and aligned to 8-byte offset. 389 * 390 * Queue, RPTR and WPTR can come from the same object, as long as the size 391 * and alignment related requirements are met. 392 */ 393 __u64 wptr_va; 394 /** 395 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow 396 * the GPU to uniquely define and identify a usermode queue. 397 * 398 * MQD data can be of different size for different GPU IP/engine and 399 * their respective versions/revisions, so this points to a __u64 * 400 * which holds IP specific MQD of this usermode queue. 401 */ 402 __u64 mqd; 403 /** 404 * @size: size of MQD data in bytes, it must match the MQD structure 405 * size of the respective engine/revision defined in UAPI for ex, for 406 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). 407 */ 408 __u64 mqd_size; 409 }; 410 411 /* The structure to carry output of userqueue ops */ 412 struct drm_amdgpu_userq_out { 413 /** 414 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique 415 * queue ID to represent the newly created userqueue in the system, otherwise 416 * it should be ignored. 417 */ 418 __u32 queue_id; 419 __u32 _pad; 420 }; 421 422 union drm_amdgpu_userq { 423 struct drm_amdgpu_userq_in in; 424 struct drm_amdgpu_userq_out out; 425 }; 426 427 /* GFX V11 IP specific MQD parameters */ 428 struct drm_amdgpu_userq_mqd_gfx11 { 429 /** 430 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. 431 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 432 */ 433 __u64 shadow_va; 434 /** 435 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 436 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 437 */ 438 __u64 csa_va; 439 }; 440 441 /* GFX V11 SDMA IP specific MQD parameters */ 442 struct drm_amdgpu_userq_mqd_sdma_gfx11 { 443 /** 444 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 445 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 446 * to get the size. 447 */ 448 __u64 csa_va; 449 }; 450 451 /* GFX V11 Compute IP specific MQD parameters */ 452 struct drm_amdgpu_userq_mqd_compute_gfx11 { 453 /** 454 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. 455 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 456 * to get the size. 457 */ 458 __u64 eop_va; 459 }; 460 461 /* userq signal/wait ioctl */ 462 struct drm_amdgpu_userq_signal { 463 /** 464 * @queue_id: Queue handle used by the userq fence creation function 465 * to retrieve the WPTR. 466 */ 467 __u32 queue_id; 468 __u32 pad; 469 /** 470 * @syncobj_handles: The list of syncobj handles submitted by the user queue 471 * job to be signaled. 472 */ 473 __u64 syncobj_handles; 474 /** 475 * @num_syncobj_handles: A count that represents the number of syncobj handles in 476 * @syncobj_handles. 477 */ 478 __u64 num_syncobj_handles; 479 /** 480 * @bo_read_handles: The list of BO handles that the submitted user queue job 481 * is using for read only. This will update BO fences in the kernel. 482 */ 483 __u64 bo_read_handles; 484 /** 485 * @bo_write_handles: The list of BO handles that the submitted user queue job 486 * is using for write only. This will update BO fences in the kernel. 487 */ 488 __u64 bo_write_handles; 489 /** 490 * @num_bo_read_handles: A count that represents the number of read BO handles in 491 * @bo_read_handles. 492 */ 493 __u32 num_bo_read_handles; 494 /** 495 * @num_bo_write_handles: A count that represents the number of write BO handles in 496 * @bo_write_handles. 497 */ 498 __u32 num_bo_write_handles; 499 500 }; 501 502 struct drm_amdgpu_userq_fence_info { 503 /** 504 * @va: A gpu address allocated for each queue which stores the 505 * read pointer (RPTR) value. 506 */ 507 __u64 va; 508 /** 509 * @value: A 64 bit value represents the write pointer (WPTR) of the 510 * queue commands which compared with the RPTR value to signal the 511 * fences. 512 */ 513 __u64 value; 514 }; 515 516 struct drm_amdgpu_userq_wait { 517 /** 518 * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the 519 * wait queue and maintain the fence driver references in it. 520 */ 521 __u32 waitq_id; 522 __u32 pad; 523 /** 524 * @syncobj_handles: The list of syncobj handles submitted by the user queue 525 * job to get the va/value pairs. 526 */ 527 __u64 syncobj_handles; 528 /** 529 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by 530 * the user queue job to get the va/value pairs at given @syncobj_timeline_points. 531 */ 532 __u64 syncobj_timeline_handles; 533 /** 534 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the 535 * user queue job for the corresponding @syncobj_timeline_handles. 536 */ 537 __u64 syncobj_timeline_points; 538 /** 539 * @bo_read_handles: The list of read BO handles submitted by the user queue 540 * job to get the va/value pairs. 541 */ 542 __u64 bo_read_handles; 543 /** 544 * @bo_write_handles: The list of write BO handles submitted by the user queue 545 * job to get the va/value pairs. 546 */ 547 __u64 bo_write_handles; 548 /** 549 * @num_syncobj_timeline_handles: A count that represents the number of timeline 550 * syncobj handles in @syncobj_timeline_handles. 551 */ 552 __u16 num_syncobj_timeline_handles; 553 /** 554 * @num_fences: This field can be used both as input and output. As input it defines 555 * the maximum number of fences that can be returned and as output it will specify 556 * how many fences were actually returned from the ioctl. 557 */ 558 __u16 num_fences; 559 /** 560 * @num_syncobj_handles: A count that represents the number of syncobj handles in 561 * @syncobj_handles. 562 */ 563 __u32 num_syncobj_handles; 564 /** 565 * @num_bo_read_handles: A count that represents the number of read BO handles in 566 * @bo_read_handles. 567 */ 568 __u32 num_bo_read_handles; 569 /** 570 * @num_bo_write_handles: A count that represents the number of write BO handles in 571 * @bo_write_handles. 572 */ 573 __u32 num_bo_write_handles; 574 /** 575 * @out_fences: The field is a return value from the ioctl containing the list of 576 * address/value pairs to wait for. 577 */ 578 __u64 out_fences; 579 }; 580 581 /* vm ioctl */ 582 #define AMDGPU_VM_OP_RESERVE_VMID 1 583 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 584 585 struct drm_amdgpu_vm_in { 586 /** AMDGPU_VM_OP_* */ 587 __u32 op; 588 __u32 flags; 589 }; 590 591 struct drm_amdgpu_vm_out { 592 /** For future use, no flags defined so far */ 593 __u64 flags; 594 }; 595 596 union drm_amdgpu_vm { 597 struct drm_amdgpu_vm_in in; 598 struct drm_amdgpu_vm_out out; 599 }; 600 601 /* sched ioctl */ 602 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 603 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 604 605 struct drm_amdgpu_sched_in { 606 /* AMDGPU_SCHED_OP_* */ 607 __u32 op; 608 __u32 fd; 609 /** AMDGPU_CTX_PRIORITY_* */ 610 __s32 priority; 611 __u32 ctx_id; 612 }; 613 614 union drm_amdgpu_sched { 615 struct drm_amdgpu_sched_in in; 616 }; 617 618 /* 619 * This is not a reliable API and you should expect it to fail for any 620 * number of reasons and have fallback path that do not use userptr to 621 * perform any operation. 622 */ 623 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 624 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 625 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 626 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 627 628 struct drm_amdgpu_gem_userptr { 629 __u64 addr; 630 __u64 size; 631 /* AMDGPU_GEM_USERPTR_* */ 632 __u32 flags; 633 /* Resulting GEM handle */ 634 __u32 handle; 635 }; 636 637 /* SI-CI-VI: */ 638 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 639 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 640 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 641 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 642 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 643 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 644 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 645 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 646 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 647 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 648 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 649 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 650 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 651 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 652 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 653 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 654 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 655 656 /* GFX9 - GFX11: */ 657 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 658 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 659 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 660 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 661 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 662 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 663 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 664 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 665 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 666 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 667 #define AMDGPU_TILING_SCANOUT_SHIFT 63 668 #define AMDGPU_TILING_SCANOUT_MASK 0x1 669 670 /* GFX12 and later: */ 671 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 672 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 673 /* These are DCC recompression setting for memory management: */ 674 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 675 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 676 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 677 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 678 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 679 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 680 681 /* Set/Get helpers for tiling flags. */ 682 #define AMDGPU_TILING_SET(field, value) \ 683 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 684 #define AMDGPU_TILING_GET(value, field) \ 685 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 686 687 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 688 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 689 690 /** The same structure is shared for input/output */ 691 struct drm_amdgpu_gem_metadata { 692 /** GEM Object handle */ 693 __u32 handle; 694 /** Do we want get or set metadata */ 695 __u32 op; 696 struct { 697 /** For future use, no flags defined so far */ 698 __u64 flags; 699 /** family specific tiling info */ 700 __u64 tiling_info; 701 __u32 data_size_bytes; 702 __u32 data[64]; 703 } data; 704 }; 705 706 struct drm_amdgpu_gem_mmap_in { 707 /** the GEM object handle */ 708 __u32 handle; 709 __u32 _pad; 710 }; 711 712 struct drm_amdgpu_gem_mmap_out { 713 /** mmap offset from the vma offset manager */ 714 __u64 addr_ptr; 715 }; 716 717 union drm_amdgpu_gem_mmap { 718 struct drm_amdgpu_gem_mmap_in in; 719 struct drm_amdgpu_gem_mmap_out out; 720 }; 721 722 struct drm_amdgpu_gem_wait_idle_in { 723 /** GEM object handle */ 724 __u32 handle; 725 /** For future use, no flags defined so far */ 726 __u32 flags; 727 /** Absolute timeout to wait */ 728 __u64 timeout; 729 }; 730 731 struct drm_amdgpu_gem_wait_idle_out { 732 /** BO status: 0 - BO is idle, 1 - BO is busy */ 733 __u32 status; 734 /** Returned current memory domain */ 735 __u32 domain; 736 }; 737 738 union drm_amdgpu_gem_wait_idle { 739 struct drm_amdgpu_gem_wait_idle_in in; 740 struct drm_amdgpu_gem_wait_idle_out out; 741 }; 742 743 struct drm_amdgpu_wait_cs_in { 744 /* Command submission handle 745 * handle equals 0 means none to wait for 746 * handle equals ~0ull means wait for the latest sequence number 747 */ 748 __u64 handle; 749 /** Absolute timeout to wait */ 750 __u64 timeout; 751 __u32 ip_type; 752 __u32 ip_instance; 753 __u32 ring; 754 __u32 ctx_id; 755 }; 756 757 struct drm_amdgpu_wait_cs_out { 758 /** CS status: 0 - CS completed, 1 - CS still busy */ 759 __u64 status; 760 }; 761 762 union drm_amdgpu_wait_cs { 763 struct drm_amdgpu_wait_cs_in in; 764 struct drm_amdgpu_wait_cs_out out; 765 }; 766 767 struct drm_amdgpu_fence { 768 __u32 ctx_id; 769 __u32 ip_type; 770 __u32 ip_instance; 771 __u32 ring; 772 __u64 seq_no; 773 }; 774 775 struct drm_amdgpu_wait_fences_in { 776 /** This points to uint64_t * which points to fences */ 777 __u64 fences; 778 __u32 fence_count; 779 __u32 wait_all; 780 __u64 timeout_ns; 781 }; 782 783 struct drm_amdgpu_wait_fences_out { 784 __u32 status; 785 __u32 first_signaled; 786 }; 787 788 union drm_amdgpu_wait_fences { 789 struct drm_amdgpu_wait_fences_in in; 790 struct drm_amdgpu_wait_fences_out out; 791 }; 792 793 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 794 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 795 796 /* Sets or returns a value associated with a buffer. */ 797 struct drm_amdgpu_gem_op { 798 /** GEM object handle */ 799 __u32 handle; 800 /** AMDGPU_GEM_OP_* */ 801 __u32 op; 802 /** Input or return value */ 803 __u64 value; 804 }; 805 806 #define AMDGPU_VA_OP_MAP 1 807 #define AMDGPU_VA_OP_UNMAP 2 808 #define AMDGPU_VA_OP_CLEAR 3 809 #define AMDGPU_VA_OP_REPLACE 4 810 811 /* Delay the page table update till the next CS */ 812 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 813 814 /* Mapping flags */ 815 /* readable mapping */ 816 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 817 /* writable mapping */ 818 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 819 /* executable mapping, new for VI */ 820 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 821 /* partially resident texture */ 822 #define AMDGPU_VM_PAGE_PRT (1 << 4) 823 /* MTYPE flags use bit 5 to 8 */ 824 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 825 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 826 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 827 /* Use Non Coherent MTYPE instead of default MTYPE */ 828 #define AMDGPU_VM_MTYPE_NC (1 << 5) 829 /* Use Write Combine MTYPE instead of default MTYPE */ 830 #define AMDGPU_VM_MTYPE_WC (2 << 5) 831 /* Use Cache Coherent MTYPE instead of default MTYPE */ 832 #define AMDGPU_VM_MTYPE_CC (3 << 5) 833 /* Use UnCached MTYPE instead of default MTYPE */ 834 #define AMDGPU_VM_MTYPE_UC (4 << 5) 835 /* Use Read Write MTYPE instead of default MTYPE */ 836 #define AMDGPU_VM_MTYPE_RW (5 << 5) 837 /* don't allocate MALL */ 838 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 839 840 struct drm_amdgpu_gem_va { 841 /** GEM object handle */ 842 __u32 handle; 843 __u32 _pad; 844 /** AMDGPU_VA_OP_* */ 845 __u32 operation; 846 /** AMDGPU_VM_PAGE_* */ 847 __u32 flags; 848 /** va address to assign . Must be correctly aligned.*/ 849 __u64 va_address; 850 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 851 __u64 offset_in_bo; 852 /** Specify mapping size. Must be correctly aligned. */ 853 __u64 map_size; 854 /** 855 * vm_timeline_point is a sequence number used to add new timeline point. 856 */ 857 __u64 vm_timeline_point; 858 /** 859 * The vm page table update fence is installed in given vm_timeline_syncobj_out 860 * at vm_timeline_point. 861 */ 862 __u32 vm_timeline_syncobj_out; 863 /** the number of syncobj handles in @input_fence_syncobj_handles */ 864 __u32 num_syncobj_handles; 865 /** Array of sync object handle to wait for given input fences */ 866 __u64 input_fence_syncobj_handles; 867 }; 868 869 #define AMDGPU_HW_IP_GFX 0 870 #define AMDGPU_HW_IP_COMPUTE 1 871 #define AMDGPU_HW_IP_DMA 2 872 #define AMDGPU_HW_IP_UVD 3 873 #define AMDGPU_HW_IP_VCE 4 874 #define AMDGPU_HW_IP_UVD_ENC 5 875 #define AMDGPU_HW_IP_VCN_DEC 6 876 /* 877 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 878 * both encoding and decoding jobs. 879 */ 880 #define AMDGPU_HW_IP_VCN_ENC 7 881 #define AMDGPU_HW_IP_VCN_JPEG 8 882 #define AMDGPU_HW_IP_VPE 9 883 #define AMDGPU_HW_IP_NUM 10 884 885 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 886 887 #define AMDGPU_CHUNK_ID_IB 0x01 888 #define AMDGPU_CHUNK_ID_FENCE 0x02 889 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 890 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 891 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 892 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 893 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 894 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 895 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 896 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 897 898 struct drm_amdgpu_cs_chunk { 899 __u32 chunk_id; 900 __u32 length_dw; 901 __u64 chunk_data; 902 }; 903 904 struct drm_amdgpu_cs_in { 905 /** Rendering context id */ 906 __u32 ctx_id; 907 /** Handle of resource list associated with CS */ 908 __u32 bo_list_handle; 909 __u32 num_chunks; 910 __u32 flags; 911 /** this points to __u64 * which point to cs chunks */ 912 __u64 chunks; 913 }; 914 915 struct drm_amdgpu_cs_out { 916 __u64 handle; 917 }; 918 919 union drm_amdgpu_cs { 920 struct drm_amdgpu_cs_in in; 921 struct drm_amdgpu_cs_out out; 922 }; 923 924 /* Specify flags to be used for IB */ 925 926 /* This IB should be submitted to CE */ 927 #define AMDGPU_IB_FLAG_CE (1<<0) 928 929 /* Preamble flag, which means the IB could be dropped if no context switch */ 930 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 931 932 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 933 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 934 935 /* The IB fence should do the L2 writeback but not invalidate any shader 936 * caches (L2/vL1/sL1/I$). */ 937 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 938 939 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 940 * This will reset wave ID counters for the IB. 941 */ 942 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 943 944 /* Flag the IB as secure (TMZ) 945 */ 946 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 947 948 /* Tell KMD to flush and invalidate caches 949 */ 950 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 951 952 struct drm_amdgpu_cs_chunk_ib { 953 __u32 _pad; 954 /** AMDGPU_IB_FLAG_* */ 955 __u32 flags; 956 /** Virtual address to begin IB execution */ 957 __u64 va_start; 958 /** Size of submission */ 959 __u32 ib_bytes; 960 /** HW IP to submit to */ 961 __u32 ip_type; 962 /** HW IP index of the same type to submit to */ 963 __u32 ip_instance; 964 /** Ring index to submit to */ 965 __u32 ring; 966 }; 967 968 struct drm_amdgpu_cs_chunk_dep { 969 __u32 ip_type; 970 __u32 ip_instance; 971 __u32 ring; 972 __u32 ctx_id; 973 __u64 handle; 974 }; 975 976 struct drm_amdgpu_cs_chunk_fence { 977 __u32 handle; 978 __u32 offset; 979 }; 980 981 struct drm_amdgpu_cs_chunk_sem { 982 __u32 handle; 983 }; 984 985 struct drm_amdgpu_cs_chunk_syncobj { 986 __u32 handle; 987 __u32 flags; 988 __u64 point; 989 }; 990 991 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 992 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 993 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 994 995 union drm_amdgpu_fence_to_handle { 996 struct { 997 struct drm_amdgpu_fence fence; 998 __u32 what; 999 __u32 pad; 1000 } in; 1001 struct { 1002 __u32 handle; 1003 } out; 1004 }; 1005 1006 struct drm_amdgpu_cs_chunk_data { 1007 union { 1008 struct drm_amdgpu_cs_chunk_ib ib_data; 1009 struct drm_amdgpu_cs_chunk_fence fence_data; 1010 }; 1011 }; 1012 1013 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 1014 1015 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 1016 __u64 shadow_va; 1017 __u64 csa_va; 1018 __u64 gds_va; 1019 __u64 flags; 1020 }; 1021 1022 /* 1023 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 1024 * 1025 */ 1026 #define AMDGPU_IDS_FLAGS_FUSION 0x1 1027 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 1028 #define AMDGPU_IDS_FLAGS_TMZ 0x4 1029 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 1030 1031 /* 1032 * Query h/w info: Flag identifying VF/PF/PT mode 1033 * 1034 */ 1035 #define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 1036 #define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 1037 #define AMDGPU_IDS_FLAGS_MODE_PF 0x0 1038 #define AMDGPU_IDS_FLAGS_MODE_VF 0x1 1039 #define AMDGPU_IDS_FLAGS_MODE_PT 0x2 1040 1041 /* indicate if acceleration can be working */ 1042 #define AMDGPU_INFO_ACCEL_WORKING 0x00 1043 /* get the crtc_id from the mode object id? */ 1044 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 1045 /* query hw IP info */ 1046 #define AMDGPU_INFO_HW_IP_INFO 0x02 1047 /* query hw IP instance count for the specified type */ 1048 #define AMDGPU_INFO_HW_IP_COUNT 0x03 1049 /* timestamp for GL_ARB_timer_query */ 1050 #define AMDGPU_INFO_TIMESTAMP 0x05 1051 /* Query the firmware version */ 1052 #define AMDGPU_INFO_FW_VERSION 0x0e 1053 /* Subquery id: Query VCE firmware version */ 1054 #define AMDGPU_INFO_FW_VCE 0x1 1055 /* Subquery id: Query UVD firmware version */ 1056 #define AMDGPU_INFO_FW_UVD 0x2 1057 /* Subquery id: Query GMC firmware version */ 1058 #define AMDGPU_INFO_FW_GMC 0x03 1059 /* Subquery id: Query GFX ME firmware version */ 1060 #define AMDGPU_INFO_FW_GFX_ME 0x04 1061 /* Subquery id: Query GFX PFP firmware version */ 1062 #define AMDGPU_INFO_FW_GFX_PFP 0x05 1063 /* Subquery id: Query GFX CE firmware version */ 1064 #define AMDGPU_INFO_FW_GFX_CE 0x06 1065 /* Subquery id: Query GFX RLC firmware version */ 1066 #define AMDGPU_INFO_FW_GFX_RLC 0x07 1067 /* Subquery id: Query GFX MEC firmware version */ 1068 #define AMDGPU_INFO_FW_GFX_MEC 0x08 1069 /* Subquery id: Query SMC firmware version */ 1070 #define AMDGPU_INFO_FW_SMC 0x0a 1071 /* Subquery id: Query SDMA firmware version */ 1072 #define AMDGPU_INFO_FW_SDMA 0x0b 1073 /* Subquery id: Query PSP SOS firmware version */ 1074 #define AMDGPU_INFO_FW_SOS 0x0c 1075 /* Subquery id: Query PSP ASD firmware version */ 1076 #define AMDGPU_INFO_FW_ASD 0x0d 1077 /* Subquery id: Query VCN firmware version */ 1078 #define AMDGPU_INFO_FW_VCN 0x0e 1079 /* Subquery id: Query GFX RLC SRLC firmware version */ 1080 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 1081 /* Subquery id: Query GFX RLC SRLG firmware version */ 1082 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 1083 /* Subquery id: Query GFX RLC SRLS firmware version */ 1084 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 1085 /* Subquery id: Query DMCU firmware version */ 1086 #define AMDGPU_INFO_FW_DMCU 0x12 1087 #define AMDGPU_INFO_FW_TA 0x13 1088 /* Subquery id: Query DMCUB firmware version */ 1089 #define AMDGPU_INFO_FW_DMCUB 0x14 1090 /* Subquery id: Query TOC firmware version */ 1091 #define AMDGPU_INFO_FW_TOC 0x15 1092 /* Subquery id: Query CAP firmware version */ 1093 #define AMDGPU_INFO_FW_CAP 0x16 1094 /* Subquery id: Query GFX RLCP firmware version */ 1095 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 1096 /* Subquery id: Query GFX RLCV firmware version */ 1097 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 1098 /* Subquery id: Query MES_KIQ firmware version */ 1099 #define AMDGPU_INFO_FW_MES_KIQ 0x19 1100 /* Subquery id: Query MES firmware version */ 1101 #define AMDGPU_INFO_FW_MES 0x1a 1102 /* Subquery id: Query IMU firmware version */ 1103 #define AMDGPU_INFO_FW_IMU 0x1b 1104 /* Subquery id: Query VPE firmware version */ 1105 #define AMDGPU_INFO_FW_VPE 0x1c 1106 1107 /* number of bytes moved for TTM migration */ 1108 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 1109 /* the used VRAM size */ 1110 #define AMDGPU_INFO_VRAM_USAGE 0x10 1111 /* the used GTT size */ 1112 #define AMDGPU_INFO_GTT_USAGE 0x11 1113 /* Information about GDS, etc. resource configuration */ 1114 #define AMDGPU_INFO_GDS_CONFIG 0x13 1115 /* Query information about VRAM and GTT domains */ 1116 #define AMDGPU_INFO_VRAM_GTT 0x14 1117 /* Query information about register in MMR address space*/ 1118 #define AMDGPU_INFO_READ_MMR_REG 0x15 1119 /* Query information about device: rev id, family, etc. */ 1120 #define AMDGPU_INFO_DEV_INFO 0x16 1121 /* visible vram usage */ 1122 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 1123 /* number of TTM buffer evictions */ 1124 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 1125 /* Query memory about VRAM and GTT domains */ 1126 #define AMDGPU_INFO_MEMORY 0x19 1127 /* Query vce clock table */ 1128 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 1129 /* Query vbios related information */ 1130 #define AMDGPU_INFO_VBIOS 0x1B 1131 /* Subquery id: Query vbios size */ 1132 #define AMDGPU_INFO_VBIOS_SIZE 0x1 1133 /* Subquery id: Query vbios image */ 1134 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 1135 /* Subquery id: Query vbios info */ 1136 #define AMDGPU_INFO_VBIOS_INFO 0x3 1137 /* Query UVD handles */ 1138 #define AMDGPU_INFO_NUM_HANDLES 0x1C 1139 /* Query sensor related information */ 1140 #define AMDGPU_INFO_SENSOR 0x1D 1141 /* Subquery id: Query GPU shader clock */ 1142 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 1143 /* Subquery id: Query GPU memory clock */ 1144 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 1145 /* Subquery id: Query GPU temperature */ 1146 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 1147 /* Subquery id: Query GPU load */ 1148 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 1149 /* Subquery id: Query average GPU power */ 1150 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 1151 /* Subquery id: Query northbridge voltage */ 1152 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 1153 /* Subquery id: Query graphics voltage */ 1154 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 1155 /* Subquery id: Query GPU stable pstate shader clock */ 1156 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 1157 /* Subquery id: Query GPU stable pstate memory clock */ 1158 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 1159 /* Subquery id: Query GPU peak pstate shader clock */ 1160 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 1161 /* Subquery id: Query GPU peak pstate memory clock */ 1162 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 1163 /* Subquery id: Query input GPU power */ 1164 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 1165 /* Number of VRAM page faults on CPU access. */ 1166 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 1167 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 1168 /* query ras mask of enabled features*/ 1169 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 1170 /* RAS MASK: UMC (VRAM) */ 1171 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 1172 /* RAS MASK: SDMA */ 1173 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 1174 /* RAS MASK: GFX */ 1175 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 1176 /* RAS MASK: MMHUB */ 1177 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 1178 /* RAS MASK: ATHUB */ 1179 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 1180 /* RAS MASK: PCIE */ 1181 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 1182 /* RAS MASK: HDP */ 1183 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 1184 /* RAS MASK: XGMI */ 1185 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 1186 /* RAS MASK: DF */ 1187 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 1188 /* RAS MASK: SMN */ 1189 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 1190 /* RAS MASK: SEM */ 1191 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 1192 /* RAS MASK: MP0 */ 1193 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 1194 /* RAS MASK: MP1 */ 1195 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 1196 /* RAS MASK: FUSE */ 1197 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 1198 /* query video encode/decode caps */ 1199 #define AMDGPU_INFO_VIDEO_CAPS 0x21 1200 /* Subquery id: Decode */ 1201 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 1202 /* Subquery id: Encode */ 1203 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 1204 /* Query the max number of IBs per gang per submission */ 1205 #define AMDGPU_INFO_MAX_IBS 0x22 1206 /* query last page fault info */ 1207 #define AMDGPU_INFO_GPUVM_FAULT 0x23 1208 /* query FW object size and alignment */ 1209 #define AMDGPU_INFO_UQ_FW_AREAS 0x24 1210 1211 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 1212 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 1213 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 1214 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 1215 1216 struct drm_amdgpu_query_fw { 1217 /** AMDGPU_INFO_FW_* */ 1218 __u32 fw_type; 1219 /** 1220 * Index of the IP if there are more IPs of 1221 * the same type. 1222 */ 1223 __u32 ip_instance; 1224 /** 1225 * Index of the engine. Whether this is used depends 1226 * on the firmware type. (e.g. MEC, SDMA) 1227 */ 1228 __u32 index; 1229 __u32 _pad; 1230 }; 1231 1232 /* Input structure for the INFO ioctl */ 1233 struct drm_amdgpu_info { 1234 /* Where the return value will be stored */ 1235 __u64 return_pointer; 1236 /* The size of the return value. Just like "size" in "snprintf", 1237 * it limits how many bytes the kernel can write. */ 1238 __u32 return_size; 1239 /* The query request id. */ 1240 __u32 query; 1241 1242 union { 1243 struct { 1244 __u32 id; 1245 __u32 _pad; 1246 } mode_crtc; 1247 1248 struct { 1249 /** AMDGPU_HW_IP_* */ 1250 __u32 type; 1251 /** 1252 * Index of the IP if there are more IPs of the same 1253 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 1254 */ 1255 __u32 ip_instance; 1256 } query_hw_ip; 1257 1258 struct { 1259 __u32 dword_offset; 1260 /** number of registers to read */ 1261 __u32 count; 1262 __u32 instance; 1263 /** For future use, no flags defined so far */ 1264 __u32 flags; 1265 } read_mmr_reg; 1266 1267 struct drm_amdgpu_query_fw query_fw; 1268 1269 struct { 1270 __u32 type; 1271 __u32 offset; 1272 } vbios_info; 1273 1274 struct { 1275 __u32 type; 1276 } sensor_info; 1277 1278 struct { 1279 __u32 type; 1280 } video_cap; 1281 }; 1282 }; 1283 1284 struct drm_amdgpu_info_gds { 1285 /** GDS GFX partition size */ 1286 __u32 gds_gfx_partition_size; 1287 /** GDS compute partition size */ 1288 __u32 compute_partition_size; 1289 /** total GDS memory size */ 1290 __u32 gds_total_size; 1291 /** GWS size per GFX partition */ 1292 __u32 gws_per_gfx_partition; 1293 /** GSW size per compute partition */ 1294 __u32 gws_per_compute_partition; 1295 /** OA size per GFX partition */ 1296 __u32 oa_per_gfx_partition; 1297 /** OA size per compute partition */ 1298 __u32 oa_per_compute_partition; 1299 __u32 _pad; 1300 }; 1301 1302 struct drm_amdgpu_info_vram_gtt { 1303 __u64 vram_size; 1304 __u64 vram_cpu_accessible_size; 1305 __u64 gtt_size; 1306 }; 1307 1308 struct drm_amdgpu_heap_info { 1309 /** max. physical memory */ 1310 __u64 total_heap_size; 1311 1312 /** Theoretical max. available memory in the given heap */ 1313 __u64 usable_heap_size; 1314 1315 /** 1316 * Number of bytes allocated in the heap. This includes all processes 1317 * and private allocations in the kernel. It changes when new buffers 1318 * are allocated, freed, and moved. It cannot be larger than 1319 * heap_size. 1320 */ 1321 __u64 heap_usage; 1322 1323 /** 1324 * Theoretical possible max. size of buffer which 1325 * could be allocated in the given heap 1326 */ 1327 __u64 max_allocation; 1328 }; 1329 1330 struct drm_amdgpu_memory_info { 1331 struct drm_amdgpu_heap_info vram; 1332 struct drm_amdgpu_heap_info cpu_accessible_vram; 1333 struct drm_amdgpu_heap_info gtt; 1334 }; 1335 1336 struct drm_amdgpu_info_firmware { 1337 __u32 ver; 1338 __u32 feature; 1339 }; 1340 1341 struct drm_amdgpu_info_vbios { 1342 __u8 name[64]; 1343 __u8 vbios_pn[64]; 1344 __u32 version; 1345 __u32 pad; 1346 __u8 vbios_ver_str[32]; 1347 __u8 date[32]; 1348 }; 1349 1350 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1351 #define AMDGPU_VRAM_TYPE_GDDR1 1 1352 #define AMDGPU_VRAM_TYPE_DDR2 2 1353 #define AMDGPU_VRAM_TYPE_GDDR3 3 1354 #define AMDGPU_VRAM_TYPE_GDDR4 4 1355 #define AMDGPU_VRAM_TYPE_GDDR5 5 1356 #define AMDGPU_VRAM_TYPE_HBM 6 1357 #define AMDGPU_VRAM_TYPE_DDR3 7 1358 #define AMDGPU_VRAM_TYPE_DDR4 8 1359 #define AMDGPU_VRAM_TYPE_GDDR6 9 1360 #define AMDGPU_VRAM_TYPE_DDR5 10 1361 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1362 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1363 1364 struct drm_amdgpu_info_device { 1365 /** PCI Device ID */ 1366 __u32 device_id; 1367 /** Internal chip revision: A0, A1, etc.) */ 1368 __u32 chip_rev; 1369 __u32 external_rev; 1370 /** Revision id in PCI Config space */ 1371 __u32 pci_rev; 1372 __u32 family; 1373 __u32 num_shader_engines; 1374 __u32 num_shader_arrays_per_engine; 1375 /* in KHz */ 1376 __u32 gpu_counter_freq; 1377 __u64 max_engine_clock; 1378 __u64 max_memory_clock; 1379 /* cu information */ 1380 __u32 cu_active_number; 1381 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1382 __u32 cu_ao_mask; 1383 __u32 cu_bitmap[4][4]; 1384 /** Render backend pipe mask. One render backend is CB+DB. */ 1385 __u32 enabled_rb_pipes_mask; 1386 __u32 num_rb_pipes; 1387 __u32 num_hw_gfx_contexts; 1388 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1389 __u32 pcie_gen; 1390 __u64 ids_flags; 1391 /** Starting virtual address for UMDs. */ 1392 __u64 virtual_address_offset; 1393 /** The maximum virtual address */ 1394 __u64 virtual_address_max; 1395 /** Required alignment of virtual addresses. */ 1396 __u32 virtual_address_alignment; 1397 /** Page table entry - fragment size */ 1398 __u32 pte_fragment_size; 1399 __u32 gart_page_size; 1400 /** constant engine ram size*/ 1401 __u32 ce_ram_size; 1402 /** video memory type info*/ 1403 __u32 vram_type; 1404 /** video memory bit width*/ 1405 __u32 vram_bit_width; 1406 /* vce harvesting instance */ 1407 __u32 vce_harvest_config; 1408 /* gfx double offchip LDS buffers */ 1409 __u32 gc_double_offchip_lds_buf; 1410 /* NGG Primitive Buffer */ 1411 __u64 prim_buf_gpu_addr; 1412 /* NGG Position Buffer */ 1413 __u64 pos_buf_gpu_addr; 1414 /* NGG Control Sideband */ 1415 __u64 cntl_sb_buf_gpu_addr; 1416 /* NGG Parameter Cache */ 1417 __u64 param_buf_gpu_addr; 1418 __u32 prim_buf_size; 1419 __u32 pos_buf_size; 1420 __u32 cntl_sb_buf_size; 1421 __u32 param_buf_size; 1422 /* wavefront size*/ 1423 __u32 wave_front_size; 1424 /* shader visible vgprs*/ 1425 __u32 num_shader_visible_vgprs; 1426 /* CU per shader array*/ 1427 __u32 num_cu_per_sh; 1428 /* number of tcc blocks*/ 1429 __u32 num_tcc_blocks; 1430 /* gs vgt table depth*/ 1431 __u32 gs_vgt_table_depth; 1432 /* gs primitive buffer depth*/ 1433 __u32 gs_prim_buffer_depth; 1434 /* max gs wavefront per vgt*/ 1435 __u32 max_gs_waves_per_vgt; 1436 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1437 __u32 pcie_num_lanes; 1438 /* always on cu bitmap */ 1439 __u32 cu_ao_bitmap[4][4]; 1440 /** Starting high virtual address for UMDs. */ 1441 __u64 high_va_offset; 1442 /** The maximum high virtual address */ 1443 __u64 high_va_max; 1444 /* gfx10 pa_sc_tile_steering_override */ 1445 __u32 pa_sc_tile_steering_override; 1446 /* disabled TCCs */ 1447 __u64 tcc_disabled_mask; 1448 __u64 min_engine_clock; 1449 __u64 min_memory_clock; 1450 /* The following fields are only set on gfx11+, older chips set 0. */ 1451 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1452 __u32 num_sqc_per_wgp; 1453 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1454 __u32 sqc_inst_cache_size; 1455 __u32 gl1c_cache_size; 1456 __u32 gl2c_cache_size; 1457 __u64 mall_size; /* AKA infinity cache */ 1458 /* high 32 bits of the rb pipes mask */ 1459 __u32 enabled_rb_pipes_mask_hi; 1460 /* shadow area size for gfx11 */ 1461 __u32 shadow_size; 1462 /* shadow area base virtual alignment for gfx11 */ 1463 __u32 shadow_alignment; 1464 /* context save area size for gfx11 */ 1465 __u32 csa_size; 1466 /* context save area base virtual alignment for gfx11 */ 1467 __u32 csa_alignment; 1468 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ 1469 __u32 userq_ip_mask; 1470 __u32 pad; 1471 }; 1472 1473 struct drm_amdgpu_info_hw_ip { 1474 /** Version of h/w IP */ 1475 __u32 hw_ip_version_major; 1476 __u32 hw_ip_version_minor; 1477 /** Capabilities */ 1478 __u64 capabilities_flags; 1479 /** command buffer address start alignment*/ 1480 __u32 ib_start_alignment; 1481 /** command buffer size alignment*/ 1482 __u32 ib_size_alignment; 1483 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1484 __u32 available_rings; 1485 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1486 __u32 ip_discovery_version; 1487 }; 1488 1489 /* GFX metadata BO sizes and alignment info (in bytes) */ 1490 struct drm_amdgpu_info_uq_fw_areas_gfx { 1491 /* shadow area size */ 1492 __u32 shadow_size; 1493 /* shadow area base virtual mem alignment */ 1494 __u32 shadow_alignment; 1495 /* context save area size */ 1496 __u32 csa_size; 1497 /* context save area base virtual mem alignment */ 1498 __u32 csa_alignment; 1499 }; 1500 1501 /* IP specific metadata related information used in the 1502 * subquery AMDGPU_INFO_UQ_FW_AREAS 1503 */ 1504 struct drm_amdgpu_info_uq_fw_areas { 1505 union { 1506 struct drm_amdgpu_info_uq_fw_areas_gfx gfx; 1507 }; 1508 }; 1509 1510 struct drm_amdgpu_info_num_handles { 1511 /** Max handles as supported by firmware for UVD */ 1512 __u32 uvd_max_handles; 1513 /** Handles currently in use for UVD */ 1514 __u32 uvd_used_handles; 1515 }; 1516 1517 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1518 1519 struct drm_amdgpu_info_vce_clock_table_entry { 1520 /** System clock */ 1521 __u32 sclk; 1522 /** Memory clock */ 1523 __u32 mclk; 1524 /** VCE clock */ 1525 __u32 eclk; 1526 __u32 pad; 1527 }; 1528 1529 struct drm_amdgpu_info_vce_clock_table { 1530 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1531 __u32 num_valid_entries; 1532 __u32 pad; 1533 }; 1534 1535 /* query video encode/decode caps */ 1536 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1537 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1538 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1539 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1540 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1541 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1542 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1543 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1544 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1545 1546 struct drm_amdgpu_info_video_codec_info { 1547 __u32 valid; 1548 __u32 max_width; 1549 __u32 max_height; 1550 __u32 max_pixels_per_frame; 1551 __u32 max_level; 1552 __u32 pad; 1553 }; 1554 1555 struct drm_amdgpu_info_video_caps { 1556 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1557 }; 1558 1559 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1560 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1561 #define AMDGPU_VMHUB_TYPE_GFX 0 1562 #define AMDGPU_VMHUB_TYPE_MM0 1 1563 #define AMDGPU_VMHUB_TYPE_MM1 2 1564 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1565 #define AMDGPU_VMHUB_IDX_SHIFT 8 1566 1567 struct drm_amdgpu_info_gpuvm_fault { 1568 __u64 addr; 1569 __u32 status; 1570 __u32 vmhub; 1571 }; 1572 1573 /* 1574 * Supported GPU families 1575 */ 1576 #define AMDGPU_FAMILY_UNKNOWN 0 1577 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1578 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1579 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1580 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1581 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1582 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1583 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1584 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1585 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1586 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1587 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1588 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1589 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1590 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1591 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1592 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1593 1594 #if defined(__cplusplus) 1595 } 1596 #endif 1597 1598 #endif 1599
Indexes created Tue Aug 04 00:24:20 UTC 2026