1 /* $NetBSD: vmwgfx_drv.c,v 1.7 2022/10/25 23:35:43 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: GPL-2.0 OR MIT 4 /************************************************************************** 5 * 6 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 24 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 25 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 26 * USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 **************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: vmwgfx_drv.c,v 1.7 2022/10/25 23:35:43 riastradh Exp $"); 32 33 #include <linux/console.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 38 #include <drm/drm_drv.h> 39 #include <drm/drm_ioctl.h> 40 #include <drm/drm_sysfs.h> 41 #include <drm/ttm/ttm_bo_driver.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_placement.h> 44 45 #include "ttm_object.h" 46 #include "vmwgfx_binding.h" 47 #include "vmwgfx_drv.h" 48 49 #include <linux/nbsd-namespace.h> 50 51 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 52 #define VMWGFX_CHIP_SVGAII 0 53 #define VMW_FB_RESERVATION 0 54 55 #define VMW_MIN_INITIAL_WIDTH 800 56 #define VMW_MIN_INITIAL_HEIGHT 600 57 58 #ifndef VMWGFX_GIT_VERSION 59 #define VMWGFX_GIT_VERSION "Unknown" 60 #endif 61 62 #define VMWGFX_REPO "In Tree" 63 64 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 65 66 67 /** 68 * Fully encoded drm commands. Might move to vmw_drm.h 69 */ 70 71 #define DRM_IOCTL_VMW_GET_PARAM \ 72 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 73 struct drm_vmw_getparam_arg) 74 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 75 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 76 union drm_vmw_alloc_dmabuf_arg) 77 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 79 struct drm_vmw_unref_dmabuf_arg) 80 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 81 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 82 struct drm_vmw_cursor_bypass_arg) 83 84 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 86 struct drm_vmw_control_stream_arg) 87 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 88 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 89 struct drm_vmw_stream_arg) 90 #define DRM_IOCTL_VMW_UNREF_STREAM \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 92 struct drm_vmw_stream_arg) 93 94 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 95 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 96 struct drm_vmw_context_arg) 97 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 99 struct drm_vmw_context_arg) 100 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 102 union drm_vmw_surface_create_arg) 103 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 105 struct drm_vmw_surface_arg) 106 #define DRM_IOCTL_VMW_REF_SURFACE \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 108 union drm_vmw_surface_reference_arg) 109 #define DRM_IOCTL_VMW_EXECBUF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 111 struct drm_vmw_execbuf_arg) 112 #define DRM_IOCTL_VMW_GET_3D_CAP \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 114 struct drm_vmw_get_3d_cap_arg) 115 #define DRM_IOCTL_VMW_FENCE_WAIT \ 116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 117 struct drm_vmw_fence_wait_arg) 118 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 119 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 120 struct drm_vmw_fence_signaled_arg) 121 #define DRM_IOCTL_VMW_FENCE_UNREF \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 123 struct drm_vmw_fence_arg) 124 #define DRM_IOCTL_VMW_FENCE_EVENT \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 126 struct drm_vmw_fence_event_arg) 127 #define DRM_IOCTL_VMW_PRESENT \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 129 struct drm_vmw_present_arg) 130 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 131 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 132 struct drm_vmw_present_readback_arg) 133 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 135 struct drm_vmw_update_layout_arg) 136 #define DRM_IOCTL_VMW_CREATE_SHADER \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 138 struct drm_vmw_shader_create_arg) 139 #define DRM_IOCTL_VMW_UNREF_SHADER \ 140 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 141 struct drm_vmw_shader_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 144 union drm_vmw_gb_surface_create_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 147 union drm_vmw_gb_surface_reference_arg) 148 #define DRM_IOCTL_VMW_SYNCCPU \ 149 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 150 struct drm_vmw_synccpu_arg) 151 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 153 struct drm_vmw_context_arg) 154 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 156 union drm_vmw_gb_surface_create_ext_arg) 157 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 158 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 159 union drm_vmw_gb_surface_reference_ext_arg) 160 #define DRM_IOCTL_VMW_MSG \ 161 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 162 struct drm_vmw_msg_arg) 163 164 /** 165 * The core DRM version of this macro doesn't account for 166 * DRM_COMMAND_BASE. 167 */ 168 169 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 170 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 171 172 /** 173 * Ioctl definitions. 174 */ 175 176 static const struct drm_ioctl_desc vmw_ioctls[] = { 177 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 178 DRM_RENDER_ALLOW), 179 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 180 DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 184 vmw_kms_cursor_bypass_ioctl, 185 DRM_MASTER), 186 187 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 188 DRM_MASTER), 189 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 190 DRM_MASTER), 191 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 192 DRM_MASTER), 193 194 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 199 DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 201 DRM_RENDER_ALLOW), 202 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 203 DRM_RENDER_ALLOW), 204 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 205 DRM_RENDER_ALLOW), 206 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 207 DRM_RENDER_ALLOW), 208 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 209 vmw_fence_obj_signaled_ioctl, 210 DRM_RENDER_ALLOW), 211 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 212 DRM_RENDER_ALLOW), 213 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 214 DRM_RENDER_ALLOW), 215 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 216 DRM_RENDER_ALLOW), 217 218 /* these allow direct access to the framebuffers mark as master only */ 219 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 220 DRM_MASTER | DRM_AUTH), 221 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 222 vmw_present_readback_ioctl, 223 DRM_MASTER | DRM_AUTH), 224 /* 225 * The permissions of the below ioctl are overridden in 226 * vmw_generic_ioctl(). We require either 227 * DRM_MASTER or capable(CAP_SYS_ADMIN). 228 */ 229 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 230 vmw_kms_update_layout_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 233 vmw_shader_define_ioctl, 234 DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 236 vmw_shader_destroy_ioctl, 237 DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 239 vmw_gb_surface_define_ioctl, 240 DRM_RENDER_ALLOW), 241 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 242 vmw_gb_surface_reference_ioctl, 243 DRM_RENDER_ALLOW), 244 VMW_IOCTL_DEF(VMW_SYNCCPU, 245 vmw_user_bo_synccpu_ioctl, 246 DRM_RENDER_ALLOW), 247 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 248 vmw_extended_context_define_ioctl, 249 DRM_RENDER_ALLOW), 250 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 251 vmw_gb_surface_define_ext_ioctl, 252 DRM_RENDER_ALLOW), 253 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 254 vmw_gb_surface_reference_ext_ioctl, 255 DRM_RENDER_ALLOW), 256 VMW_IOCTL_DEF(VMW_MSG, 257 vmw_msg_ioctl, 258 DRM_RENDER_ALLOW), 259 }; 260 261 static const struct pci_device_id vmw_pci_id_list[] = { 262 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 263 {0, 0, 0} 264 }; 265 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 266 267 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 268 static int vmw_force_iommu; 269 static int vmw_restrict_iommu; 270 static int vmw_force_coherent; 271 static int vmw_restrict_dma_mask; 272 static int vmw_assume_16bpp; 273 274 #ifndef __NetBSD__ 275 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 276 #endif 277 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 278 void *ptr); 279 280 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 281 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 282 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 283 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 284 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 285 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 286 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 287 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 288 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 289 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 290 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 291 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 292 293 294 static void vmw_print_capabilities2(uint32_t capabilities2) 295 { 296 DRM_INFO("Capabilities2:\n"); 297 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 298 DRM_INFO(" Grow oTable.\n"); 299 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 300 DRM_INFO(" IntraSurface copy.\n"); 301 } 302 303 static void vmw_print_capabilities(uint32_t capabilities) 304 { 305 DRM_INFO("Capabilities:\n"); 306 if (capabilities & SVGA_CAP_RECT_COPY) 307 DRM_INFO(" Rect copy.\n"); 308 if (capabilities & SVGA_CAP_CURSOR) 309 DRM_INFO(" Cursor.\n"); 310 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 311 DRM_INFO(" Cursor bypass.\n"); 312 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 313 DRM_INFO(" Cursor bypass 2.\n"); 314 if (capabilities & SVGA_CAP_8BIT_EMULATION) 315 DRM_INFO(" 8bit emulation.\n"); 316 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 317 DRM_INFO(" Alpha cursor.\n"); 318 if (capabilities & SVGA_CAP_3D) 319 DRM_INFO(" 3D.\n"); 320 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 321 DRM_INFO(" Extended Fifo.\n"); 322 if (capabilities & SVGA_CAP_MULTIMON) 323 DRM_INFO(" Multimon.\n"); 324 if (capabilities & SVGA_CAP_PITCHLOCK) 325 DRM_INFO(" Pitchlock.\n"); 326 if (capabilities & SVGA_CAP_IRQMASK) 327 DRM_INFO(" Irq mask.\n"); 328 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 329 DRM_INFO(" Display Topology.\n"); 330 if (capabilities & SVGA_CAP_GMR) 331 DRM_INFO(" GMR.\n"); 332 if (capabilities & SVGA_CAP_TRACES) 333 DRM_INFO(" Traces.\n"); 334 if (capabilities & SVGA_CAP_GMR2) 335 DRM_INFO(" GMR2.\n"); 336 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 337 DRM_INFO(" Screen Object 2.\n"); 338 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 339 DRM_INFO(" Command Buffers.\n"); 340 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 341 DRM_INFO(" Command Buffers 2.\n"); 342 if (capabilities & SVGA_CAP_GBOBJECTS) 343 DRM_INFO(" Guest Backed Resources.\n"); 344 if (capabilities & SVGA_CAP_DX) 345 DRM_INFO(" DX Features.\n"); 346 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 347 DRM_INFO(" HP Command Queue.\n"); 348 } 349 350 /** 351 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 352 * 353 * @dev_priv: A device private structure. 354 * 355 * This function creates a small buffer object that holds the query 356 * result for dummy queries emitted as query barriers. 357 * The function will then map the first page and initialize a pending 358 * occlusion query result structure, Finally it will unmap the buffer. 359 * No interruptible waits are done within this function. 360 * 361 * Returns an error if bo creation or initialization fails. 362 */ 363 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 364 { 365 int ret; 366 struct vmw_buffer_object *vbo; 367 struct ttm_bo_kmap_obj map; 368 volatile SVGA3dQueryResult *result; 369 bool dummy; 370 371 /* 372 * Create the vbo as pinned, so that a tryreserve will 373 * immediately succeed. This is because we're the only 374 * user of the bo currently. 375 */ 376 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 377 if (!vbo) 378 return -ENOMEM; 379 380 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 381 &vmw_sys_ne_placement, false, 382 &vmw_bo_bo_free); 383 if (unlikely(ret != 0)) 384 return ret; 385 386 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 387 BUG_ON(ret != 0); 388 vmw_bo_pin_reserved(vbo, true); 389 390 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 391 if (likely(ret == 0)) { 392 result = ttm_kmap_obj_virtual(&map, &dummy); 393 result->totalSize = sizeof(*result); 394 result->state = SVGA3D_QUERYSTATE_PENDING; 395 result->result32 = 0xff; 396 ttm_bo_kunmap(&map); 397 } 398 vmw_bo_pin_reserved(vbo, false); 399 ttm_bo_unreserve(&vbo->base); 400 401 if (unlikely(ret != 0)) { 402 DRM_ERROR("Dummy query buffer map failed.\n"); 403 vmw_bo_unreference(&vbo); 404 } else 405 dev_priv->dummy_query_bo = vbo; 406 407 return ret; 408 } 409 410 /** 411 * vmw_request_device_late - Perform late device setup 412 * 413 * @dev_priv: Pointer to device private. 414 * 415 * This function performs setup of otables and enables large command 416 * buffer submission. These tasks are split out to a separate function 417 * because it reverts vmw_release_device_early and is intended to be used 418 * by an error path in the hibernation code. 419 */ 420 static int vmw_request_device_late(struct vmw_private *dev_priv) 421 { 422 int ret; 423 424 if (dev_priv->has_mob) { 425 ret = vmw_otables_setup(dev_priv); 426 if (unlikely(ret != 0)) { 427 DRM_ERROR("Unable to initialize " 428 "guest Memory OBjects.\n"); 429 return ret; 430 } 431 } 432 433 if (dev_priv->cman) { 434 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 435 256*4096, 2*4096); 436 if (ret) { 437 struct vmw_cmdbuf_man *man = dev_priv->cman; 438 439 dev_priv->cman = NULL; 440 vmw_cmdbuf_man_destroy(man); 441 } 442 } 443 444 return 0; 445 } 446 447 static int vmw_request_device(struct vmw_private *dev_priv) 448 { 449 int ret; 450 451 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 452 if (unlikely(ret != 0)) { 453 DRM_ERROR("Unable to initialize FIFO.\n"); 454 return ret; 455 } 456 vmw_fence_fifo_up(dev_priv->fman); 457 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 458 if (IS_ERR(dev_priv->cman)) { 459 dev_priv->cman = NULL; 460 dev_priv->has_dx = false; 461 } 462 463 ret = vmw_request_device_late(dev_priv); 464 if (ret) 465 goto out_no_mob; 466 467 ret = vmw_dummy_query_bo_create(dev_priv); 468 if (unlikely(ret != 0)) 469 goto out_no_query_bo; 470 471 return 0; 472 473 out_no_query_bo: 474 if (dev_priv->cman) 475 vmw_cmdbuf_remove_pool(dev_priv->cman); 476 if (dev_priv->has_mob) { 477 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 478 vmw_otables_takedown(dev_priv); 479 } 480 if (dev_priv->cman) 481 vmw_cmdbuf_man_destroy(dev_priv->cman); 482 out_no_mob: 483 vmw_fence_fifo_down(dev_priv->fman); 484 vmw_fifo_release(dev_priv, &dev_priv->fifo); 485 return ret; 486 } 487 488 /** 489 * vmw_release_device_early - Early part of fifo takedown. 490 * 491 * @dev_priv: Pointer to device private struct. 492 * 493 * This is the first part of command submission takedown, to be called before 494 * buffer management is taken down. 495 */ 496 static void vmw_release_device_early(struct vmw_private *dev_priv) 497 { 498 /* 499 * Previous destructions should've released 500 * the pinned bo. 501 */ 502 503 BUG_ON(dev_priv->pinned_bo != NULL); 504 505 vmw_bo_unreference(&dev_priv->dummy_query_bo); 506 if (dev_priv->cman) 507 vmw_cmdbuf_remove_pool(dev_priv->cman); 508 509 if (dev_priv->has_mob) { 510 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 511 vmw_otables_takedown(dev_priv); 512 } 513 } 514 515 /** 516 * vmw_release_device_late - Late part of fifo takedown. 517 * 518 * @dev_priv: Pointer to device private struct. 519 * 520 * This is the last part of the command submission takedown, to be called when 521 * command submission is no longer needed. It may wait on pending fences. 522 */ 523 static void vmw_release_device_late(struct vmw_private *dev_priv) 524 { 525 vmw_fence_fifo_down(dev_priv->fman); 526 if (dev_priv->cman) 527 vmw_cmdbuf_man_destroy(dev_priv->cman); 528 529 vmw_fifo_release(dev_priv, &dev_priv->fifo); 530 } 531 532 /** 533 * Sets the initial_[width|height] fields on the given vmw_private. 534 * 535 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 536 * clamping the value to fb_max_[width|height] fields and the 537 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 538 * If the values appear to be invalid, set them to 539 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 540 */ 541 static void vmw_get_initial_size(struct vmw_private *dev_priv) 542 { 543 uint32_t width; 544 uint32_t height; 545 546 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 547 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 548 549 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 550 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 551 552 if (width > dev_priv->fb_max_width || 553 height > dev_priv->fb_max_height) { 554 555 /* 556 * This is a host error and shouldn't occur. 557 */ 558 559 width = VMW_MIN_INITIAL_WIDTH; 560 height = VMW_MIN_INITIAL_HEIGHT; 561 } 562 563 dev_priv->initial_width = width; 564 dev_priv->initial_height = height; 565 } 566 567 /** 568 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 569 * system. 570 * 571 * @dev_priv: Pointer to a struct vmw_private 572 * 573 * This functions tries to determine what actions need to be taken by the 574 * driver to make system pages visible to the device. 575 * If this function decides that DMA is not possible, it returns -EINVAL. 576 * The driver may then try to disable features of the device that require 577 * DMA. 578 */ 579 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 580 { 581 static const char *names[vmw_dma_map_max] = { 582 [vmw_dma_phys] = "Using physical TTM page addresses.", 583 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 584 [vmw_dma_map_populate] = "Caching DMA mappings.", 585 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 586 587 if (vmw_force_coherent) 588 dev_priv->map_mode = vmw_dma_alloc_coherent; 589 else if (vmw_restrict_iommu) 590 dev_priv->map_mode = vmw_dma_map_bind; 591 else 592 dev_priv->map_mode = vmw_dma_map_populate; 593 594 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 595 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 596 return -EINVAL; 597 598 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 599 return 0; 600 } 601 602 /** 603 * vmw_dma_masks - set required page- and dma masks 604 * 605 * @dev: Pointer to struct drm-device 606 * 607 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 608 * restriction also for 64-bit systems. 609 */ 610 static int vmw_dma_masks(struct vmw_private *dev_priv) 611 { 612 struct drm_device *dev = dev_priv->dev; 613 int ret = 0; 614 615 #ifdef __NetBSD__ 616 ret = drm_limit_dma_space(dev, 0, __BITS(63,0)); 617 #else 618 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 619 #endif 620 if (dev_priv->map_mode != vmw_dma_phys && 621 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 622 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 623 #ifdef __NetBSD__ 624 return drm_limit_dma_space(dev, 0, __BITS(43,0)); 625 #else 626 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 627 #endif 628 } 629 630 return ret; 631 } 632 633 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 634 { 635 struct vmw_private *dev_priv; 636 int ret; 637 uint32_t svga_id; 638 enum vmw_res_type i; 639 bool refuse_dma = false; 640 char host_log[100] = {0}; 641 642 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 643 if (unlikely(!dev_priv)) { 644 DRM_ERROR("Failed allocating a device private struct.\n"); 645 return -ENOMEM; 646 } 647 648 pci_set_master(dev->pdev); 649 650 dev_priv->dev = dev; 651 dev_priv->vmw_chipset = chipset; 652 dev_priv->last_read_seqno = (uint32_t) -100; 653 mutex_init(&dev_priv->cmdbuf_mutex); 654 mutex_init(&dev_priv->release_mutex); 655 mutex_init(&dev_priv->binding_mutex); 656 mutex_init(&dev_priv->global_kms_state_mutex); 657 ttm_lock_init(&dev_priv->reservation_sem); 658 spin_lock_init(&dev_priv->resource_lock); 659 spin_lock_init(&dev_priv->hw_lock); 660 spin_lock_init(&dev_priv->waiter_lock); 661 spin_lock_init(&dev_priv->cap_lock); 662 spin_lock_init(&dev_priv->svga_lock); 663 spin_lock_init(&dev_priv->cursor_lock); 664 665 for (i = vmw_res_context; i < vmw_res_max; ++i) { 666 idr_init(&dev_priv->res_idr[i]); 667 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 668 } 669 670 DRM_INIT_WAITQUEUE(&dev_priv->fence_queue, "vmwgfence"); 671 spin_lock_init(&dev_priv->fence_lock); 672 DRM_INIT_WAITQUEUE(&dev_priv->fifo_queue, "vmwgfifo"); 673 spin_lock_init(&dev_priv->fifo_lock); 674 dev_priv->fence_queue_waiters = 0; 675 dev_priv->fifo_queue_waiters = 0; 676 677 dev_priv->used_memory_size = 0; 678 679 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 680 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 681 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 682 683 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 684 685 dev_priv->enable_fb = enable_fbdev; 686 687 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 688 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 689 if (svga_id != SVGA_ID_2) { 690 ret = -ENOSYS; 691 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 692 goto out_err0; 693 } 694 695 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 696 697 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 698 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 699 } 700 701 702 ret = vmw_dma_select_mode(dev_priv); 703 if (unlikely(ret != 0)) { 704 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 705 refuse_dma = true; 706 } 707 708 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 709 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 710 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 711 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 712 713 vmw_get_initial_size(dev_priv); 714 715 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 716 dev_priv->max_gmr_ids = 717 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 718 dev_priv->max_gmr_pages = 719 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 720 dev_priv->memory_size = 721 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 722 dev_priv->memory_size -= dev_priv->vram_size; 723 } else { 724 /* 725 * An arbitrary limit of 512MiB on surface 726 * memory. But all HWV8 hardware supports GMR2. 727 */ 728 dev_priv->memory_size = 512*1024*1024; 729 } 730 dev_priv->max_mob_pages = 0; 731 dev_priv->max_mob_size = 0; 732 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 733 uint64_t mem_size = 734 vmw_read(dev_priv, 735 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 736 737 /* 738 * Workaround for low memory 2D VMs to compensate for the 739 * allocation taken by fbdev 740 */ 741 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 742 mem_size *= 3; 743 744 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 745 dev_priv->prim_bb_mem = 746 vmw_read(dev_priv, 747 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 748 dev_priv->max_mob_size = 749 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 750 dev_priv->stdu_max_width = 751 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 752 dev_priv->stdu_max_height = 753 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 754 755 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 756 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 757 dev_priv->texture_max_width = vmw_read(dev_priv, 758 SVGA_REG_DEV_CAP); 759 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 760 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 761 dev_priv->texture_max_height = vmw_read(dev_priv, 762 SVGA_REG_DEV_CAP); 763 } else { 764 dev_priv->texture_max_width = 8192; 765 dev_priv->texture_max_height = 8192; 766 dev_priv->prim_bb_mem = dev_priv->vram_size; 767 } 768 769 vmw_print_capabilities(dev_priv->capabilities); 770 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 771 vmw_print_capabilities2(dev_priv->capabilities2); 772 773 ret = vmw_dma_masks(dev_priv); 774 if (unlikely(ret != 0)) 775 goto out_err0; 776 777 #ifndef __NetBSD__ /* XXX set bus_dma maxsegsz? */ 778 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 779 SCATTERLIST_MAX_SEGMENT)); 780 #endif 781 782 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 783 DRM_INFO("Max GMR ids is %u\n", 784 (unsigned)dev_priv->max_gmr_ids); 785 DRM_INFO("Max number of GMR pages is %u\n", 786 (unsigned)dev_priv->max_gmr_pages); 787 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 788 (unsigned)dev_priv->memory_size / 1024); 789 } 790 DRM_INFO("Maximum display memory size is %u kiB\n", 791 dev_priv->prim_bb_mem / 1024); 792 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 793 dev_priv->vram_start, dev_priv->vram_size / 1024); 794 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 795 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 796 797 #ifdef __NetBSD__ 798 dev_priv->mmio_bst = dev->bst; 799 if (bus_space_map(dev_priv->mmio_bst, dev_priv->mmio_start, 800 dev_priv->mmio_size, BUS_SPACE_MAP_LINEAR, 801 &dev_priv->mmio_bsh) == 0) { 802 dev_priv->mmio_virt = bus_space_vaddr(dev_priv->mmio_bst, 803 dev_priv->mmio_bsh); 804 } else { 805 dev_priv->mmio_virt = NULL; 806 } 807 #else 808 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 809 dev_priv->mmio_size, MEMREMAP_WB); 810 #endif 811 812 if (unlikely(dev_priv->mmio_virt == NULL)) { 813 ret = -ENOMEM; 814 DRM_ERROR("Failed mapping MMIO.\n"); 815 goto out_err0; 816 } 817 818 #ifdef __NetBSD__ 819 dev_priv->iot = dev->pdev->pd_pa.pa_iot; 820 821 /* XXX errno NetBSD->Linux */ 822 ret = -bus_space_map(dev_priv->iot, dev_priv->io_start, VMWGFX_IOSIZE, 823 0, &dev_priv->ioh); 824 if (ret) { 825 DRM_ERROR("Failed mapping IO ports.\n"); 826 goto out_err3; 827 } 828 #endif 829 830 /* Need mmio memory to check for fifo pitchlock cap. */ 831 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 832 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 833 !vmw_fifo_have_pitchlock(dev_priv)) { 834 ret = -ENOSYS; 835 DRM_ERROR("Hardware has no pitchlock\n"); 836 goto out_err4; 837 } 838 839 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 840 &vmw_prime_dmabuf_ops); 841 842 if (unlikely(dev_priv->tdev == NULL)) { 843 DRM_ERROR("Unable to initialize TTM object management.\n"); 844 ret = -ENOMEM; 845 goto out_err4; 846 } 847 848 dev->dev_private = dev_priv; 849 850 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 851 dev_priv->stealth = (ret != 0); 852 if (dev_priv->stealth) { 853 /** 854 * Request at least the mmio PCI resource. 855 */ 856 857 DRM_INFO("It appears like vesafb is loaded. " 858 "Ignore above error if any.\n"); 859 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 860 if (unlikely(ret != 0)) { 861 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 862 goto out_no_device; 863 } 864 } 865 866 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 867 #ifdef __NetBSD__ 868 ret = vmw_irq_install(dev, 0); 869 #else 870 ret = vmw_irq_install(dev, dev->pdev->irq); 871 #endif 872 if (ret != 0) { 873 DRM_ERROR("Failed installing irq: %d\n", ret); 874 goto out_no_irq; 875 } 876 } 877 878 dev_priv->fman = vmw_fence_manager_init(dev_priv); 879 if (unlikely(dev_priv->fman == NULL)) { 880 ret = -ENOMEM; 881 goto out_no_fman; 882 } 883 884 drm_vma_offset_manager_init(&dev_priv->vma_manager, 885 DRM_FILE_PAGE_OFFSET_START, 886 DRM_FILE_PAGE_OFFSET_SIZE); 887 ret = ttm_bo_device_init(&dev_priv->bdev, 888 &vmw_bo_driver, 889 #ifdef __NetBSD__ 890 dev->bst, 891 dev->dmat, 892 #else 893 dev->anon_inode->i_mapping, 894 #endif 895 &dev_priv->vma_manager, 896 false); 897 if (unlikely(ret != 0)) { 898 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 899 goto out_no_bdev; 900 } 901 902 /* 903 * Enable VRAM, but initially don't use it until SVGA is enabled and 904 * unhidden. 905 */ 906 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 907 (dev_priv->vram_size >> PAGE_SHIFT)); 908 if (unlikely(ret != 0)) { 909 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 910 goto out_no_vram; 911 } 912 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 913 914 dev_priv->has_gmr = true; 915 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 916 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 917 VMW_PL_GMR) != 0) { 918 DRM_INFO("No GMR memory available. " 919 "Graphics memory resources are very limited.\n"); 920 dev_priv->has_gmr = false; 921 } 922 923 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 924 dev_priv->has_mob = true; 925 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 926 VMW_PL_MOB) != 0) { 927 DRM_INFO("No MOB memory available. " 928 "3D will be disabled.\n"); 929 dev_priv->has_mob = false; 930 } 931 } 932 933 if (dev_priv->has_mob) { 934 spin_lock(&dev_priv->cap_lock); 935 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 936 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 937 spin_unlock(&dev_priv->cap_lock); 938 } 939 940 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 941 ret = vmw_kms_init(dev_priv); 942 if (unlikely(ret != 0)) 943 goto out_no_kms; 944 vmw_overlay_init(dev_priv); 945 946 ret = vmw_request_device(dev_priv); 947 if (ret) 948 goto out_no_fifo; 949 950 if (dev_priv->has_dx) { 951 /* 952 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 953 * support 954 */ 955 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 956 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 957 SVGA3D_DEVCAP_SM41); 958 dev_priv->has_sm4_1 = vmw_read(dev_priv, 959 SVGA_REG_DEV_CAP); 960 } 961 } 962 963 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 964 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 965 ? "yes." : "no."); 966 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 967 968 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 969 VMWGFX_REPO, VMWGFX_GIT_VERSION); 970 vmw_host_log(host_log); 971 972 memset(host_log, 0, sizeof(host_log)); 973 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 974 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 975 VMWGFX_DRIVER_PATCHLEVEL); 976 vmw_host_log(host_log); 977 978 if (dev_priv->enable_fb) { 979 vmw_fifo_resource_inc(dev_priv); 980 vmw_svga_enable(dev_priv); 981 vmw_fb_init(dev_priv); 982 } 983 984 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 985 register_pm_notifier(&dev_priv->pm_nb); 986 987 return 0; 988 989 out_no_fifo: 990 vmw_overlay_close(dev_priv); 991 vmw_kms_close(dev_priv); 992 out_no_kms: 993 if (dev_priv->has_mob) 994 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 995 if (dev_priv->has_gmr) 996 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 997 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 998 out_no_vram: 999 (void)ttm_bo_device_release(&dev_priv->bdev); 1000 out_no_bdev: 1001 vmw_fence_manager_takedown(dev_priv->fman); 1002 out_no_fman: 1003 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1004 vmw_irq_uninstall(dev_priv->dev); 1005 out_no_irq: 1006 if (dev_priv->stealth) 1007 pci_release_region(dev->pdev, 2); 1008 else 1009 pci_release_regions(dev->pdev); 1010 out_no_device: 1011 ttm_object_device_release(&dev_priv->tdev); 1012 out_err4: 1013 #ifdef __NetBSD__ 1014 bus_space_unmap(dev_priv->iot, dev_priv->ioh, VMWGFX_IOSIZE); 1015 out_err3: 1016 dev_priv->mmio_virt = NULL; 1017 bus_space_unmap(dev_priv->mmio_bst, dev_priv->mmio_bsh, 1018 dev_priv->mmio_size); 1019 #else 1020 memunmap(dev_priv->mmio_virt); 1021 #endif 1022 out_err0: 1023 spin_lock_destroy(&dev_priv->fifo_lock); 1024 DRM_DESTROY_WAITQUEUE(&dev_priv->fifo_queue); 1025 spin_lock_destroy(&dev_priv->fence_lock); 1026 DRM_DESTROY_WAITQUEUE(&dev_priv->fence_queue); 1027 1028 for (i = vmw_res_context; i < vmw_res_max; ++i) 1029 idr_destroy(&dev_priv->res_idr[i]); 1030 1031 if (dev_priv->ctx.staged_bindings) 1032 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1033 kfree(dev_priv); 1034 return ret; 1035 } 1036 1037 static void vmw_driver_unload(struct drm_device *dev) 1038 { 1039 struct vmw_private *dev_priv = vmw_priv(dev); 1040 enum vmw_res_type i; 1041 1042 unregister_pm_notifier(&dev_priv->pm_nb); 1043 1044 if (dev_priv->ctx.res_ht_initialized) 1045 drm_ht_remove(&dev_priv->ctx.res_ht); 1046 vfree(dev_priv->ctx.cmd_bounce); 1047 if (dev_priv->enable_fb) { 1048 vmw_fb_off(dev_priv); 1049 vmw_fb_close(dev_priv); 1050 vmw_fifo_resource_dec(dev_priv); 1051 vmw_svga_disable(dev_priv); 1052 } 1053 1054 vmw_kms_close(dev_priv); 1055 vmw_overlay_close(dev_priv); 1056 1057 if (dev_priv->has_gmr) 1058 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 1059 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 1060 1061 vmw_release_device_early(dev_priv); 1062 if (dev_priv->has_mob) 1063 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 1064 (void) ttm_bo_device_release(&dev_priv->bdev); 1065 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1066 vmw_release_device_late(dev_priv); 1067 vmw_fence_manager_takedown(dev_priv->fman); 1068 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1069 vmw_irq_uninstall(dev_priv->dev); 1070 if (dev_priv->stealth) 1071 pci_release_region(dev->pdev, 2); 1072 else 1073 pci_release_regions(dev->pdev); 1074 1075 ttm_object_device_release(&dev_priv->tdev); 1076 #ifdef __NetBSD__ 1077 dev_priv->mmio_virt = NULL; 1078 bus_space_unmap(dev_priv->mmio_bst, dev_priv->mmio_bsh, 1079 dev_priv->mmio_size); 1080 #else 1081 memunmap(dev_priv->mmio_virt); 1082 #endif 1083 if (dev_priv->ctx.staged_bindings) 1084 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1085 1086 spin_lock_destroy(&dev_priv->fifo_lock); 1087 DRM_DESTROY_WAITQUEUE(&dev_priv->fifo_queue); 1088 spin_lock_destroy(&dev_priv->fence_lock); 1089 DRM_DESTROY_WAITQUEUE(&dev_priv->fence_queue); 1090 1091 for (i = vmw_res_context; i < vmw_res_max; ++i) 1092 idr_destroy(&dev_priv->res_idr[i]); 1093 1094 kfree(dev_priv); 1095 } 1096 1097 static void vmw_postclose(struct drm_device *dev, 1098 struct drm_file *file_priv) 1099 { 1100 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1101 1102 ttm_object_file_release(&vmw_fp->tfile); 1103 kfree(vmw_fp); 1104 } 1105 1106 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1107 { 1108 struct vmw_private *dev_priv = vmw_priv(dev); 1109 struct vmw_fpriv *vmw_fp; 1110 int ret = -ENOMEM; 1111 1112 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1113 if (unlikely(!vmw_fp)) 1114 return ret; 1115 1116 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1117 if (unlikely(vmw_fp->tfile == NULL)) 1118 goto out_no_tfile; 1119 1120 file_priv->driver_priv = vmw_fp; 1121 1122 return 0; 1123 1124 out_no_tfile: 1125 kfree(vmw_fp); 1126 return ret; 1127 } 1128 1129 #ifdef __NetBSD__ 1130 static int vmw_generic_ioctl(struct file *filp, unsigned long cmd, 1131 void *arg, 1132 int (*ioctl_func)(struct file *, unsigned long, 1133 void *)) 1134 #else 1135 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1136 unsigned long arg, 1137 long (*ioctl_func)(struct file *, unsigned int, 1138 unsigned long)) 1139 #endif 1140 { 1141 #ifdef __NetBSD__ 1142 struct drm_file *file_priv = filp->f_data; 1143 #else 1144 struct drm_file *file_priv = filp->private_data; 1145 #endif 1146 struct drm_device *dev = file_priv->minor->dev; 1147 unsigned int nr = DRM_IOCTL_NR(cmd); 1148 unsigned int flags; 1149 1150 /* 1151 * Do extra checking on driver private ioctls. 1152 */ 1153 1154 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1155 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1156 const struct drm_ioctl_desc *ioctl = 1157 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1158 1159 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1160 return ioctl_func(filp, cmd, arg); 1161 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1162 if (!drm_is_current_master(file_priv) && 1163 !capable(CAP_SYS_ADMIN)) 1164 return -EACCES; 1165 } 1166 1167 if (unlikely(ioctl->cmd != cmd)) 1168 goto out_io_encoding; 1169 1170 flags = ioctl->flags; 1171 } else if (!drm_ioctl_flags(nr, &flags)) 1172 return -EINVAL; 1173 1174 return ioctl_func(filp, cmd, arg); 1175 1176 out_io_encoding: 1177 DRM_ERROR("Invalid command format, ioctl %d\n", 1178 nr - DRM_COMMAND_BASE); 1179 1180 return -EINVAL; 1181 } 1182 1183 #ifdef __NetBSD__ 1184 static int vmw_unlocked_ioctl(struct file *filp, unsigned long cmd, void *arg) 1185 #else 1186 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1187 unsigned long arg) 1188 #endif 1189 { 1190 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1191 } 1192 1193 #ifdef CONFIG_COMPAT 1194 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1195 unsigned long arg) 1196 { 1197 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1198 } 1199 #endif 1200 1201 static int vmw_master_set(struct drm_device *dev, 1202 struct drm_file *file_priv, 1203 bool from_open) 1204 { 1205 /* 1206 * Inform a new master that the layout may have changed while 1207 * it was gone. 1208 */ 1209 if (!from_open) 1210 drm_sysfs_hotplug_event(dev); 1211 1212 return 0; 1213 } 1214 1215 static void vmw_master_drop(struct drm_device *dev, 1216 struct drm_file *file_priv) 1217 { 1218 struct vmw_private *dev_priv = vmw_priv(dev); 1219 1220 vmw_kms_legacy_hotspot_clear(dev_priv); 1221 if (!dev_priv->enable_fb) 1222 vmw_svga_disable(dev_priv); 1223 } 1224 1225 /** 1226 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1227 * 1228 * @dev_priv: Pointer to device private struct. 1229 * Needs the reservation sem to be held in non-exclusive mode. 1230 */ 1231 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1232 { 1233 spin_lock(&dev_priv->svga_lock); 1234 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1235 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1236 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1237 } 1238 spin_unlock(&dev_priv->svga_lock); 1239 } 1240 1241 /** 1242 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1243 * 1244 * @dev_priv: Pointer to device private struct. 1245 */ 1246 void vmw_svga_enable(struct vmw_private *dev_priv) 1247 { 1248 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1249 __vmw_svga_enable(dev_priv); 1250 ttm_read_unlock(&dev_priv->reservation_sem); 1251 } 1252 1253 /** 1254 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1255 * 1256 * @dev_priv: Pointer to device private struct. 1257 * Needs the reservation sem to be held in exclusive mode. 1258 * Will not empty VRAM. VRAM must be emptied by caller. 1259 */ 1260 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1261 { 1262 spin_lock(&dev_priv->svga_lock); 1263 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1264 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1265 vmw_write(dev_priv, SVGA_REG_ENABLE, 1266 SVGA_REG_ENABLE_HIDE | 1267 SVGA_REG_ENABLE_ENABLE); 1268 } 1269 spin_unlock(&dev_priv->svga_lock); 1270 } 1271 1272 /** 1273 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1274 * running. 1275 * 1276 * @dev_priv: Pointer to device private struct. 1277 * Will empty VRAM. 1278 */ 1279 void vmw_svga_disable(struct vmw_private *dev_priv) 1280 { 1281 /* 1282 * Disabling SVGA will turn off device modesetting capabilities, so 1283 * notify KMS about that so that it doesn't cache atomic state that 1284 * isn't valid anymore, for example crtcs turned on. 1285 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1286 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1287 * end up with lock order reversal. Thus, a master may actually perform 1288 * a new modeset just after we call vmw_kms_lost_device() and race with 1289 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1290 * to be inconsistent with the device, causing modesetting problems. 1291 * 1292 */ 1293 vmw_kms_lost_device(dev_priv->dev); 1294 ttm_write_lock(&dev_priv->reservation_sem, false); 1295 spin_lock(&dev_priv->svga_lock); 1296 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1297 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1298 spin_unlock(&dev_priv->svga_lock); 1299 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1300 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1301 vmw_write(dev_priv, SVGA_REG_ENABLE, 1302 SVGA_REG_ENABLE_HIDE | 1303 SVGA_REG_ENABLE_ENABLE); 1304 } else 1305 spin_unlock(&dev_priv->svga_lock); 1306 ttm_write_unlock(&dev_priv->reservation_sem); 1307 } 1308 1309 #ifndef __NetBSD__ 1310 static void vmw_remove(struct pci_dev *pdev) 1311 { 1312 struct drm_device *dev = pci_get_drvdata(pdev); 1313 1314 drm_dev_unregister(dev); 1315 vmw_driver_unload(dev); 1316 drm_dev_put(dev); 1317 pci_disable_device(pdev); 1318 } 1319 #endif 1320 1321 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1322 void *ptr) 1323 { 1324 #ifndef __NetBSD__ 1325 struct vmw_private *dev_priv = 1326 container_of(nb, struct vmw_private, pm_nb); 1327 1328 switch (val) { 1329 case PM_HIBERNATION_PREPARE: 1330 /* 1331 * Take the reservation sem in write mode, which will make sure 1332 * there are no other processes holding a buffer object 1333 * reservation, meaning we should be able to evict all buffer 1334 * objects if needed. 1335 * Once user-space processes have been frozen, we can release 1336 * the lock again. 1337 */ 1338 ttm_suspend_lock(&dev_priv->reservation_sem); 1339 dev_priv->suspend_locked = true; 1340 break; 1341 case PM_POST_HIBERNATION: 1342 case PM_POST_RESTORE: 1343 if (READ_ONCE(dev_priv->suspend_locked)) { 1344 dev_priv->suspend_locked = false; 1345 ttm_suspend_unlock(&dev_priv->reservation_sem); 1346 } 1347 break; 1348 default: 1349 break; 1350 } 1351 #endif 1352 return 0; 1353 } 1354 1355 #ifndef __NetBSD__ 1356 1357 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1358 { 1359 struct drm_device *dev = pci_get_drvdata(pdev); 1360 struct vmw_private *dev_priv = vmw_priv(dev); 1361 1362 if (dev_priv->refuse_hibernation) 1363 return -EBUSY; 1364 1365 pci_save_state(pdev); 1366 pci_disable_device(pdev); 1367 pci_set_power_state(pdev, PCI_D3hot); 1368 return 0; 1369 } 1370 1371 static int vmw_pci_resume(struct pci_dev *pdev) 1372 { 1373 pci_set_power_state(pdev, PCI_D0); 1374 pci_restore_state(pdev); 1375 return pci_enable_device(pdev); 1376 } 1377 1378 static int vmw_pm_suspend(struct device *kdev) 1379 { 1380 struct pci_dev *pdev = to_pci_dev(kdev); 1381 struct pm_message dummy; 1382 1383 dummy.event = 0; 1384 1385 return vmw_pci_suspend(pdev, dummy); 1386 } 1387 1388 static int vmw_pm_resume(struct device *kdev) 1389 { 1390 struct pci_dev *pdev = to_pci_dev(kdev); 1391 1392 return vmw_pci_resume(pdev); 1393 } 1394 1395 static int vmw_pm_freeze(struct device *kdev) 1396 { 1397 struct pci_dev *pdev = to_pci_dev(kdev); 1398 struct drm_device *dev = pci_get_drvdata(pdev); 1399 struct vmw_private *dev_priv = vmw_priv(dev); 1400 int ret; 1401 1402 /* 1403 * Unlock for vmw_kms_suspend. 1404 * No user-space processes should be running now. 1405 */ 1406 ttm_suspend_unlock(&dev_priv->reservation_sem); 1407 ret = vmw_kms_suspend(dev_priv->dev); 1408 if (ret) { 1409 ttm_suspend_lock(&dev_priv->reservation_sem); 1410 DRM_ERROR("Failed to freeze modesetting.\n"); 1411 return ret; 1412 } 1413 if (dev_priv->enable_fb) 1414 vmw_fb_off(dev_priv); 1415 1416 ttm_suspend_lock(&dev_priv->reservation_sem); 1417 vmw_execbuf_release_pinned_bo(dev_priv); 1418 vmw_resource_evict_all(dev_priv); 1419 vmw_release_device_early(dev_priv); 1420 ttm_bo_swapout_all(&dev_priv->bdev); 1421 if (dev_priv->enable_fb) 1422 vmw_fifo_resource_dec(dev_priv); 1423 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1424 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1425 if (dev_priv->enable_fb) 1426 vmw_fifo_resource_inc(dev_priv); 1427 WARN_ON(vmw_request_device_late(dev_priv)); 1428 dev_priv->suspend_locked = false; 1429 ttm_suspend_unlock(&dev_priv->reservation_sem); 1430 if (dev_priv->suspend_state) 1431 vmw_kms_resume(dev); 1432 if (dev_priv->enable_fb) 1433 vmw_fb_on(dev_priv); 1434 return -EBUSY; 1435 } 1436 1437 vmw_fence_fifo_down(dev_priv->fman); 1438 __vmw_svga_disable(dev_priv); 1439 1440 vmw_release_device_late(dev_priv); 1441 return 0; 1442 } 1443 1444 static int vmw_pm_restore(struct device *kdev) 1445 { 1446 struct pci_dev *pdev = to_pci_dev(kdev); 1447 struct drm_device *dev = pci_get_drvdata(pdev); 1448 struct vmw_private *dev_priv = vmw_priv(dev); 1449 int ret; 1450 1451 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1452 (void) vmw_read(dev_priv, SVGA_REG_ID); 1453 1454 if (dev_priv->enable_fb) 1455 vmw_fifo_resource_inc(dev_priv); 1456 1457 ret = vmw_request_device(dev_priv); 1458 if (ret) 1459 return ret; 1460 1461 if (dev_priv->enable_fb) 1462 __vmw_svga_enable(dev_priv); 1463 1464 vmw_fence_fifo_up(dev_priv->fman); 1465 dev_priv->suspend_locked = false; 1466 ttm_suspend_unlock(&dev_priv->reservation_sem); 1467 if (dev_priv->suspend_state) 1468 vmw_kms_resume(dev_priv->dev); 1469 1470 if (dev_priv->enable_fb) 1471 vmw_fb_on(dev_priv); 1472 1473 return 0; 1474 } 1475 1476 static const struct dev_pm_ops vmw_pm_ops = { 1477 .freeze = vmw_pm_freeze, 1478 .thaw = vmw_pm_restore, 1479 .restore = vmw_pm_restore, 1480 .suspend = vmw_pm_suspend, 1481 .resume = vmw_pm_resume, 1482 }; 1483 1484 static const struct file_operations vmwgfx_driver_fops = { 1485 .owner = THIS_MODULE, 1486 .open = drm_open, 1487 .release = drm_release, 1488 .unlocked_ioctl = vmw_unlocked_ioctl, 1489 .mmap = vmw_mmap, 1490 .poll = vmw_fops_poll, 1491 .read = vmw_fops_read, 1492 #if defined(CONFIG_COMPAT) 1493 .compat_ioctl = vmw_compat_ioctl, 1494 #endif 1495 .llseek = noop_llseek, 1496 }; 1497 1498 #endif 1499 1500 static struct drm_driver driver = { 1501 .driver_features = 1502 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1503 .get_vblank_counter = vmw_get_vblank_counter, 1504 .enable_vblank = vmw_enable_vblank, 1505 .disable_vblank = vmw_disable_vblank, 1506 .ioctls = vmw_ioctls, 1507 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1508 .master_set = vmw_master_set, 1509 .master_drop = vmw_master_drop, 1510 .load = vmw_driver_load, 1511 .open = vmw_driver_open, 1512 .postclose = vmw_postclose, 1513 .unload = vmw_driver_unload, 1514 1515 .dumb_create = vmw_dumb_create, 1516 .dumb_map_offset = vmw_dumb_map_offset, 1517 .dumb_destroy = vmw_dumb_destroy, 1518 1519 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1520 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1521 1522 #ifdef __NetBSD__ 1523 .ioctl_override = &vmw_unlocked_ioctl, 1524 #else 1525 .fops = &vmwgfx_driver_fops, 1526 #endif 1527 .name = VMWGFX_DRIVER_NAME, 1528 .desc = VMWGFX_DRIVER_DESC, 1529 .date = VMWGFX_DRIVER_DATE, 1530 .major = VMWGFX_DRIVER_MAJOR, 1531 .minor = VMWGFX_DRIVER_MINOR, 1532 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1533 }; 1534 1535 #ifdef __NetBSD__ 1536 1537 const struct drm_driver *const vmwgfx_driver = &driver; 1538 const struct pci_device_id *const vmwgfx_pci_ids = vmw_pci_id_list; 1539 const size_t vmwgfx_n_pci_ids = __arraycount(vmw_pci_id_list); 1540 1541 #else 1542 1543 static struct pci_driver vmw_pci_driver = { 1544 .name = VMWGFX_DRIVER_NAME, 1545 .id_table = vmw_pci_id_list, 1546 .probe = vmw_probe, 1547 .remove = vmw_remove, 1548 .driver = { 1549 .pm = &vmw_pm_ops 1550 } 1551 }; 1552 1553 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1554 { 1555 struct drm_device *dev; 1556 int ret; 1557 1558 ret = pci_enable_device(pdev); 1559 if (ret) 1560 return ret; 1561 1562 dev = drm_dev_alloc(&driver, &pdev->dev); 1563 if (IS_ERR(dev)) { 1564 ret = PTR_ERR(dev); 1565 goto err_pci_disable_device; 1566 } 1567 1568 dev->pdev = pdev; 1569 pci_set_drvdata(pdev, dev); 1570 1571 ret = vmw_driver_load(dev, ent->driver_data); 1572 if (ret) 1573 goto err_drm_dev_put; 1574 1575 ret = drm_dev_register(dev, ent->driver_data); 1576 if (ret) 1577 goto err_vmw_driver_unload; 1578 1579 return 0; 1580 1581 err_vmw_driver_unload: 1582 vmw_driver_unload(dev); 1583 err_drm_dev_put: 1584 drm_dev_put(dev); 1585 err_pci_disable_device: 1586 pci_disable_device(pdev); 1587 return ret; 1588 } 1589 1590 static int __init vmwgfx_init(void) 1591 { 1592 int ret; 1593 1594 if (vgacon_text_force()) 1595 return -EINVAL; 1596 1597 ret = pci_register_driver(&vmw_pci_driver); 1598 if (ret) 1599 DRM_ERROR("Failed initializing DRM.\n"); 1600 return ret; 1601 } 1602 1603 static void __exit vmwgfx_exit(void) 1604 { 1605 pci_unregister_driver(&vmw_pci_driver); 1606 } 1607 1608 #endif 1609 1610 module_init(vmwgfx_init); 1611 module_exit(vmwgfx_exit); 1612 1613 MODULE_AUTHOR("VMware Inc. and others"); 1614 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1615 MODULE_LICENSE("GPL and additional rights"); 1616 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1617 __stringify(VMWGFX_DRIVER_MINOR) "." 1618 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1619 "0"); 1620
Indexes created Wed Oct 01 07:09:59 GMT 2025