1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 /dts-v1/; 7 8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 12 / { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 qcom,saw = <&saw_l2>; 106 }; 107 }; 108 109 cpu0_opp_table: opp_table0 { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-48000000 { 114 opp-hz = /bits/ 64 <48000000>; 115 clock-latency-ns = <256000>; 116 }; 117 opp-200000000 { 118 opp-hz = /bits/ 64 <200000000>; 119 clock-latency-ns = <256000>; 120 }; 121 opp-500000000 { 122 opp-hz = /bits/ 64 <500000000>; 123 clock-latency-ns = <256000>; 124 }; 125 opp-716000000 { 126 opp-hz = /bits/ 64 <716000000>; 127 clock-latency-ns = <256000>; 128 }; 129 }; 130 131 memory { 132 device_type = "memory"; 133 reg = <0x0 0x0>; 134 }; 135 136 pmu { 137 compatible = "arm,cortex-a7-pmu"; 138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 139 IRQ_TYPE_LEVEL_HIGH)>; 140 }; 141 142 clocks { 143 sleep_clk: sleep_clk { 144 compatible = "fixed-clock"; 145 clock-frequency = <32768>; 146 #clock-cells = <0>; 147 }; 148 149 xo: xo { 150 compatible = "fixed-clock"; 151 clock-frequency = <48000000>; 152 #clock-cells = <0>; 153 }; 154 }; 155 156 firmware { 157 scm { 158 compatible = "qcom,scm-ipq4019"; 159 }; 160 }; 161 162 timer { 163 compatible = "arm,armv7-timer"; 164 interrupts = <1 2 0xf08>, 165 <1 3 0xf08>, 166 <1 4 0xf08>, 167 <1 1 0xf08>; 168 clock-frequency = <48000000>; 169 always-on; 170 }; 171 172 soc { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 compatible = "simple-bus"; 177 178 intc: interrupt-controller@b000000 { 179 compatible = "qcom,msm-qgic2"; 180 interrupt-controller; 181 #interrupt-cells = <3>; 182 reg = <0x0b000000 0x1000>, 183 <0x0b002000 0x1000>; 184 }; 185 186 gcc: clock-controller@1800000 { 187 compatible = "qcom,gcc-ipq4019"; 188 #clock-cells = <1>; 189 #reset-cells = <1>; 190 reg = <0x1800000 0x60000>; 191 }; 192 193 prng: rng@22000 { 194 compatible = "qcom,prng"; 195 reg = <0x22000 0x140>; 196 clocks = <&gcc GCC_PRNG_AHB_CLK>; 197 clock-names = "core"; 198 status = "disabled"; 199 }; 200 201 tlmm: pinctrl@1000000 { 202 compatible = "qcom,ipq4019-pinctrl"; 203 reg = <0x01000000 0x300000>; 204 gpio-controller; 205 gpio-ranges = <&tlmm 0 0 100>; 206 #gpio-cells = <2>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 210 }; 211 212 vqmmc: regulator@1948000 { 213 compatible = "qcom,vqmmc-ipq4019-regulator"; 214 reg = <0x01948000 0x4>; 215 regulator-name = "vqmmc"; 216 regulator-min-microvolt = <1500000>; 217 regulator-max-microvolt = <3000000>; 218 regulator-always-on; 219 status = "disabled"; 220 }; 221 222 sdhci: sdhci@7824900 { 223 compatible = "qcom,sdhci-msm-v4"; 224 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 225 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "hc_irq", "pwr_irq"; 227 bus-width = <8>; 228 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, 229 <&gcc GCC_DCD_XO_CLK>; 230 clock-names = "core", "iface", "xo"; 231 status = "disabled"; 232 }; 233 234 blsp_dma: dma@7884000 { 235 compatible = "qcom,bam-v1.7.0"; 236 reg = <0x07884000 0x23000>; 237 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 239 clock-names = "bam_clk"; 240 #dma-cells = <1>; 241 qcom,ee = <0>; 242 status = "disabled"; 243 }; 244 245 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 246 compatible = "qcom,spi-qup-v2.2.1"; 247 reg = <0x78b5000 0x600>; 248 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 250 <&gcc GCC_BLSP1_AHB_CLK>; 251 clock-names = "core", "iface"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 255 dma-names = "rx", "tx"; 256 status = "disabled"; 257 }; 258 259 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 260 compatible = "qcom,spi-qup-v2.2.1"; 261 reg = <0x78b6000 0x600>; 262 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 264 <&gcc GCC_BLSP1_AHB_CLK>; 265 clock-names = "core", "iface"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 269 dma-names = "rx", "tx"; 270 status = "disabled"; 271 }; 272 273 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 274 compatible = "qcom,i2c-qup-v2.2.1"; 275 reg = <0x78b7000 0x600>; 276 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 278 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 279 clock-names = "iface", "core"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 283 dma-names = "rx", "tx"; 284 status = "disabled"; 285 }; 286 287 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 288 compatible = "qcom,i2c-qup-v2.2.1"; 289 reg = <0x78b8000 0x600>; 290 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 292 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 293 clock-names = "iface", "core"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 297 dma-names = "rx", "tx"; 298 status = "disabled"; 299 }; 300 301 cryptobam: dma@8e04000 { 302 compatible = "qcom,bam-v1.7.0"; 303 reg = <0x08e04000 0x20000>; 304 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 306 clock-names = "bam_clk"; 307 #dma-cells = <1>; 308 qcom,ee = <1>; 309 qcom,controlled-remotely; 310 status = "disabled"; 311 }; 312 313 crypto: crypto@8e3a000 { 314 compatible = "qcom,crypto-v5.1"; 315 reg = <0x08e3a000 0x6000>; 316 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 317 <&gcc GCC_CRYPTO_AXI_CLK>, 318 <&gcc GCC_CRYPTO_CLK>; 319 clock-names = "iface", "bus", "core"; 320 dmas = <&cryptobam 2>, <&cryptobam 3>; 321 dma-names = "rx", "tx"; 322 status = "disabled"; 323 }; 324 325 acc0: clock-controller@b088000 { 326 compatible = "qcom,kpss-acc-v2"; 327 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 328 }; 329 330 acc1: clock-controller@b098000 { 331 compatible = "qcom,kpss-acc-v2"; 332 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 333 }; 334 335 acc2: clock-controller@b0a8000 { 336 compatible = "qcom,kpss-acc-v2"; 337 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 338 }; 339 340 acc3: clock-controller@b0b8000 { 341 compatible = "qcom,kpss-acc-v2"; 342 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 343 }; 344 345 saw0: regulator@b089000 { 346 compatible = "qcom,saw2"; 347 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 348 regulator; 349 }; 350 351 saw1: regulator@b099000 { 352 compatible = "qcom,saw2"; 353 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 354 regulator; 355 }; 356 357 saw2: regulator@b0a9000 { 358 compatible = "qcom,saw2"; 359 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 360 regulator; 361 }; 362 363 saw3: regulator@b0b9000 { 364 compatible = "qcom,saw2"; 365 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 366 regulator; 367 }; 368 369 saw_l2: regulator@b012000 { 370 compatible = "qcom,saw2"; 371 reg = <0xb012000 0x1000>; 372 regulator; 373 }; 374 375 blsp1_uart1: serial@78af000 { 376 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 377 reg = <0x78af000 0x200>; 378 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 379 status = "disabled"; 380 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 381 <&gcc GCC_BLSP1_AHB_CLK>; 382 clock-names = "core", "iface"; 383 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 384 dma-names = "rx", "tx"; 385 }; 386 387 blsp1_uart2: serial@78b0000 { 388 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 389 reg = <0x78b0000 0x200>; 390 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 391 status = "disabled"; 392 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 393 <&gcc GCC_BLSP1_AHB_CLK>; 394 clock-names = "core", "iface"; 395 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 396 dma-names = "rx", "tx"; 397 }; 398 399 watchdog: watchdog@b017000 { 400 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; 401 reg = <0xb017000 0x40>; 402 clocks = <&sleep_clk>; 403 timeout-sec = <10>; 404 status = "disabled"; 405 }; 406 407 restart@4ab000 { 408 compatible = "qcom,pshold"; 409 reg = <0x4ab000 0x4>; 410 }; 411 412 pcie0: pci@40000000 { 413 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; 414 reg = <0x40000000 0xf1d 415 0x40000f20 0xa8 416 0x80000 0x2000 417 0x40100000 0x1000>; 418 reg-names = "dbi", "elbi", "parf", "config"; 419 device_type = "pci"; 420 linux,pci-domain = <0>; 421 bus-range = <0x00 0xff>; 422 num-lanes = <1>; 423 #address-cells = <3>; 424 #size-cells = <2>; 425 426 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, 427 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; 428 429 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 430 interrupt-names = "msi"; 431 #interrupt-cells = <1>; 432 interrupt-map-mask = <0 0 0 0x7>; 433 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 434 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 435 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 436 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 437 clocks = <&gcc GCC_PCIE_AHB_CLK>, 438 <&gcc GCC_PCIE_AXI_M_CLK>, 439 <&gcc GCC_PCIE_AXI_S_CLK>; 440 clock-names = "aux", 441 "master_bus", 442 "slave_bus"; 443 444 resets = <&gcc PCIE_AXI_M_ARES>, 445 <&gcc PCIE_AXI_S_ARES>, 446 <&gcc PCIE_PIPE_ARES>, 447 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 448 <&gcc PCIE_AXI_S_XPU_ARES>, 449 <&gcc PCIE_PARF_XPU_ARES>, 450 <&gcc PCIE_PHY_ARES>, 451 <&gcc PCIE_AXI_M_STICKY_ARES>, 452 <&gcc PCIE_PIPE_STICKY_ARES>, 453 <&gcc PCIE_PWR_ARES>, 454 <&gcc PCIE_AHB_ARES>, 455 <&gcc PCIE_PHY_AHB_ARES>; 456 reset-names = "axi_m", 457 "axi_s", 458 "pipe", 459 "axi_m_vmid", 460 "axi_s_xpu", 461 "parf", 462 "phy", 463 "axi_m_sticky", 464 "pipe_sticky", 465 "pwr", 466 "ahb", 467 "phy_ahb"; 468 469 status = "disabled"; 470 }; 471 472 qpic_bam: dma@7984000 { 473 compatible = "qcom,bam-v1.7.0"; 474 reg = <0x7984000 0x1a000>; 475 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&gcc GCC_QPIC_CLK>; 477 clock-names = "bam_clk"; 478 #dma-cells = <1>; 479 qcom,ee = <0>; 480 status = "disabled"; 481 }; 482 483 nand: nand-controller@79b0000 { 484 compatible = "qcom,ipq4019-nand"; 485 reg = <0x79b0000 0x1000>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 clocks = <&gcc GCC_QPIC_CLK>, 489 <&gcc GCC_QPIC_AHB_CLK>; 490 clock-names = "core", "aon"; 491 492 dmas = <&qpic_bam 0>, 493 <&qpic_bam 1>, 494 <&qpic_bam 2>; 495 dma-names = "tx", "rx", "cmd"; 496 status = "disabled"; 497 498 nand@0 { 499 reg = <0>; 500 501 nand-ecc-strength = <4>; 502 nand-ecc-step-size = <512>; 503 nand-bus-width = <8>; 504 }; 505 }; 506 507 wifi0: wifi@a000000 { 508 compatible = "qcom,ipq4019-wifi"; 509 reg = <0xa000000 0x200000>; 510 resets = <&gcc WIFI0_CPU_INIT_RESET>, 511 <&gcc WIFI0_RADIO_SRIF_RESET>, 512 <&gcc WIFI0_RADIO_WARM_RESET>, 513 <&gcc WIFI0_RADIO_COLD_RESET>, 514 <&gcc WIFI0_CORE_WARM_RESET>, 515 <&gcc WIFI0_CORE_COLD_RESET>; 516 reset-names = "wifi_cpu_init", "wifi_radio_srif", 517 "wifi_radio_warm", "wifi_radio_cold", 518 "wifi_core_warm", "wifi_core_cold"; 519 clocks = <&gcc GCC_WCSS2G_CLK>, 520 <&gcc GCC_WCSS2G_REF_CLK>, 521 <&gcc GCC_WCSS2G_RTC_CLK>; 522 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 523 "wifi_wcss_rtc"; 524 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 525 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 526 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 541 interrupt-names = "msi0", "msi1", "msi2", "msi3", 542 "msi4", "msi5", "msi6", "msi7", 543 "msi8", "msi9", "msi10", "msi11", 544 "msi12", "msi13", "msi14", "msi15", 545 "legacy"; 546 status = "disabled"; 547 }; 548 549 wifi1: wifi@a800000 { 550 compatible = "qcom,ipq4019-wifi"; 551 reg = <0xa800000 0x200000>; 552 resets = <&gcc WIFI1_CPU_INIT_RESET>, 553 <&gcc WIFI1_RADIO_SRIF_RESET>, 554 <&gcc WIFI1_RADIO_WARM_RESET>, 555 <&gcc WIFI1_RADIO_COLD_RESET>, 556 <&gcc WIFI1_CORE_WARM_RESET>, 557 <&gcc WIFI1_CORE_COLD_RESET>; 558 reset-names = "wifi_cpu_init", "wifi_radio_srif", 559 "wifi_radio_warm", "wifi_radio_cold", 560 "wifi_core_warm", "wifi_core_cold"; 561 clocks = <&gcc GCC_WCSS5G_CLK>, 562 <&gcc GCC_WCSS5G_REF_CLK>, 563 <&gcc GCC_WCSS5G_RTC_CLK>; 564 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 565 "wifi_wcss_rtc"; 566 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 567 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 568 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 569 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 570 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 571 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 574 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 583 interrupt-names = "msi0", "msi1", "msi2", "msi3", 584 "msi4", "msi5", "msi6", "msi7", 585 "msi8", "msi9", "msi10", "msi11", 586 "msi12", "msi13", "msi14", "msi15", 587 "legacy"; 588 status = "disabled"; 589 }; 590 591 mdio: mdio@90000 { 592 #address-cells = <1>; 593 #size-cells = <0>; 594 compatible = "qcom,ipq4019-mdio"; 595 reg = <0x90000 0x64>; 596 status = "disabled"; 597 598 ethphy0: ethernet-phy@0 { 599 reg = <0>; 600 }; 601 602 ethphy1: ethernet-phy@1 { 603 reg = <1>; 604 }; 605 606 ethphy2: ethernet-phy@2 { 607 reg = <2>; 608 }; 609 610 ethphy3: ethernet-phy@3 { 611 reg = <3>; 612 }; 613 614 ethphy4: ethernet-phy@4 { 615 reg = <4>; 616 }; 617 }; 618 619 usb3_ss_phy: ssphy@9a000 { 620 compatible = "qcom,usb-ss-ipq4019-phy"; 621 #phy-cells = <0>; 622 reg = <0x9a000 0x800>; 623 reg-names = "phy_base"; 624 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 625 reset-names = "por_rst"; 626 status = "disabled"; 627 }; 628 629 usb3_hs_phy: hsphy@a6000 { 630 compatible = "qcom,usb-hs-ipq4019-phy"; 631 #phy-cells = <0>; 632 reg = <0xa6000 0x40>; 633 reg-names = "phy_base"; 634 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 635 reset-names = "por_rst", "srif_rst"; 636 status = "disabled"; 637 }; 638 639 usb3: usb3@8af8800 { 640 compatible = "qcom,dwc3"; 641 reg = <0x8af8800 0x100>; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 clocks = <&gcc GCC_USB3_MASTER_CLK>, 645 <&gcc GCC_USB3_SLEEP_CLK>, 646 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 647 clock-names = "master", "sleep", "mock_utmi"; 648 ranges; 649 status = "disabled"; 650 651 dwc3@8a00000 { 652 compatible = "snps,dwc3"; 653 reg = <0x8a00000 0xf8000>; 654 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 655 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 656 phy-names = "usb2-phy", "usb3-phy"; 657 dr_mode = "host"; 658 }; 659 }; 660 661 usb2_hs_phy: hsphy@a8000 { 662 compatible = "qcom,usb-hs-ipq4019-phy"; 663 #phy-cells = <0>; 664 reg = <0xa8000 0x40>; 665 reg-names = "phy_base"; 666 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 667 reset-names = "por_rst", "srif_rst"; 668 status = "disabled"; 669 }; 670 671 usb2: usb2@60f8800 { 672 compatible = "qcom,dwc3"; 673 reg = <0x60f8800 0x100>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 clocks = <&gcc GCC_USB2_MASTER_CLK>, 677 <&gcc GCC_USB2_SLEEP_CLK>, 678 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 679 clock-names = "master", "sleep", "mock_utmi"; 680 ranges; 681 status = "disabled"; 682 683 dwc3@6000000 { 684 compatible = "snps,dwc3"; 685 reg = <0x6000000 0xf8000>; 686 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 687 phys = <&usb2_hs_phy>; 688 phy-names = "usb2-phy"; 689 dr_mode = "host"; 690 }; 691 }; 692 }; 693 }; 694
Indexes created Mon Sep 29 21:09:56 GMT 2025