| /src/lib/libtelnet/ |
| auth.h | 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 int way; member in struct:XauthP
|
| /src/sys/arch/mips/mips/ |
| cache_mipsNN.c | 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
131 * If we are going to flush more than is in a way (or the stride
132 * need for that way), we are flushing everything.
139 for (size_t way = 0; way < ways; way++) { local in function:mipsNN_picache_sync_range_index
169 * If we are going to flush more than is in a way, we are flushing
179 * Invalidate each way. If the address range wraps past the end of
180 * the way, we will be invalidating in two ways but eventually things
181 * work out since the last way will wrap into the first way
183 for (size_t way = 0; way < ways; way++) { local in function:mipsNN_pdcache_wbinv_range_index
226 for (size_t way = 0; way < ways; way++) { local in function:mipsNN_sdcache_wbinv_range_index
[all...] |
| cache_r5k.c | 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
51 * - 2-way set-associative
55 * Since the R4600 is so similar (2-way set-associative, 32b/l),
136 * If we are going to flush more than is in a way (or the stride
137 * needed for that way), we are flushing everything.
144 for (size_t way = 0; way < ways; way++) { local in function:r5k_picache_sync_range_index
187 * If we are going to flush more than is in a way, we are flushing
197 * Invalidate each way. If the address range wraps past the end o
201 for (size_t way = 0; way < ways; way++) { local in function:r5k_pdcache_wbinv_range_index
[all...] |
| cache_octeon.c | 134 /* way = (0 .. 3) */
136 int way; local in function:octeon_icache_dump_all
138 for (way = 0; way < maxway; way++)
139 octeon_icache_dump_way(way);
143 octeon_icache_dump_way(int way)
150 octeon_icache_dump_index(way, index);
154 octeon_icache_dump_index(int way, int index)
156 const vaddr_t va = (way << 13) | (index << 7)
207 int way; local in function:octeon_dcache_dump_all
[all...] |
| /src/sys/arch/sh3/sh3/ |
| cache_sh3.c | 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
99 * In RAM-mode, way 2 and 3 are used as RAM.
109 sh_cache_way_size = sh_cache_size_unified / 4/*way*/;
112 /* shift for way selection (16KB/8KB) */
115 ffs(sh_cache_size_unified / (4/*way*/ * 16/*line-size*/)) - 1
145 int way; local in function:cache_sh3_op_line_16_nway
150 /* operate for each way */
151 for (way = 0; way < n; way++)
167 int way; local in function:cache_sh3_op_8lines_16_nway
[all...] |
| mmu_sh3.c | 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61 int i, way; local in function:sh3_tlb_invalidate_all
66 for (way = 0; way < SH3_MMU_WAY; ++way) {
67 a = idx | (way << SH3_MMU_WAY_SHIFT);
80 int i, way; local in function:sh3_tlb_invalidate_asid
85 for (way = 0; way < SH3_MMU_WAY; ++way) {
99 int way; local in function:sh3_tlb_invalidate_addr
130 int way; local in function:sh3_tlb_update
[all...] |
| db_interface.c | 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
292 db_printf(" [way %d]\n", i);
496 int entry, way; local in function:__db_cachedump_sh3
510 db_printf("%d-way, way-size=%dB, way-shift=%d, entry-mask=%08x, "
513 db_printf("Entry Way 0 UV Way 1 UV Way 2 UV Way 3 UV\n")
[all...] |
| /src/sys/arch/arm/arm32/ |
| arm32_tlb.c | 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
152 for (size_t way = 0; way < 2; way++) { local in function:tlb_cortex_a5_record_asids
154 __SHIFTIN(way, ARM_TLBDATAOP_WAY)
184 for (size_t way = 0; way < 2; way++) { local in function:tlb_cortex_a7_record_asids
186 __SHIFTIN(way, ARM_TLBDATAOP_WAY)
236 /* no way to view the TLB *
[all...] |
| db_machdep.c | 231 tlb_print_addr(size_t way, size_t va_index, vaddr_t vpn, paddr_t pfn)
233 db_printf("[%1zu:%02zx] 0x%05lx000 0x%05lx000", way, va_index, vpn, pfn);
277 tlb_print_cortex_a5_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1)
288 tlb_print_addr(way, va_index, vpn, pfn);
342 tlb_print_cortex_a7_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1)
351 tlb_print_addr(way, va_index, vpn, pfn);
422 for (size_t way = 0; way < 2; way++) { local in function:db_show_tlb_cmd
425 | __SHIFTIN(way, ARM_TLBDATAOP_WAY))
443 for (size_t way = 0; way < 2; way++) { local in function:db_show_tlb_cmd
[all...] |
| /src/sys/arch/hpc/stand/hpcboot/sh3/ |
| sh_mmu.cpp | 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
48 int way, kmode; local in function:MemoryManager_SHMMU::searchPage
66 for (way = 0; way < SH3_MMU_WAY; way++) {
67 entry_idx = idx | (way << SH3_MMU_WAY_SHIFT);
175 DPRINTF((TEXT(" [way %d]\n"), i));
|
| /src/sys/arch/aarch64/aarch64/ |
| cpufunc.c | 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
283 "L%d %uKB/%uB %u-way (%u set) %s %s cache\n",
315 unsigned int set, way, setshift, wayshift; local in function:ln_dcache_wb_all
320 for (way = 0; way < cunit->cache_ways; way++) {
322 x = (way << wayshift) | (set << setshift) |
333 unsigned int set, way, setshift, wayshift; local in function:ln_dcache_wbinv_all
338 for (way = 0; way < cunit->cache_ways; way++)
351 unsigned int set, way, setshift, wayshift; local in function:ln_dcache_inv_all
[all...] |
