1 /* $NetBSD: wdc.c,v 1.314 2026/04/10 13:55:59 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.314 2026/04/10 13:55:59 jakllsch Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/kmem.h> 74 #include <sys/syslog.h> 75 #include <sys/proc.h> 76 77 #include <sys/intr.h> 78 #include <sys/bus.h> 79 80 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 81 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 82 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 83 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 84 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 85 #define bus_space_read_stream_2 bus_space_read_2 86 #define bus_space_read_stream_4 bus_space_read_4 87 #define bus_space_write_stream_2 bus_space_write_2 88 #define bus_space_write_stream_4 bus_space_write_4 89 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 90 91 #include <dev/ata/atavar.h> 92 #include <dev/ata/atareg.h> 93 #include <dev/ata/satareg.h> 94 #include <dev/ata/satavar.h> 95 #include <dev/ic/wdcreg.h> 96 #include <dev/ic/wdcvar.h> 97 98 #include "locators.h" 99 100 #include "atapibus.h" 101 #include "wd.h" 102 #include "sata.h" 103 104 #define WDCDELAY 100 /* 100 microseconds */ 105 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 106 #if 0 107 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 108 #define WDCNDELAY_DEBUG 50 109 #endif 110 111 /* When polling wait that much and then kpause for 1/hz seconds */ 112 #define WDCDELAY_POLL 1 /* ms */ 113 114 /* timeout for the control commands */ 115 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 116 117 /* 118 * timeout when waiting for BSY to deassert when probing. 119 * set to 5s. From the standards this could be up to 31, but we can't 120 * wait that much at boot time, and 5s seems to be enough. 121 */ 122 #define WDC_PROBE_WAIT 5 123 124 125 #if NWD > 0 126 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 127 #else 128 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 129 const struct ata_bustype wdc_ata_bustype = { 130 .bustype_type = SCSIPI_BUSTYPE_ATA, 131 .ata_bio = NULL, 132 .ata_reset_drive = NULL, 133 .ata_reset_channel = wdc_reset_channel, 134 .ata_exec_command = wdc_exec_command, 135 .ata_get_params = NULL, 136 .ata_addref = NULL, 137 .ata_delref = NULL, 138 .ata_killpending = NULL, 139 .ata_recovery = NULL, 140 }; 141 #endif 142 143 /* Flags to wdcreset(). */ 144 #define RESET_POLL 1 145 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 146 147 static int wdcprobe1(struct ata_channel *, int); 148 static int wdcreset(struct ata_channel *, int); 149 static void __wdcerror(struct ata_channel *, const char *); 150 static int __wdcwait_reset(struct ata_channel *, int, int); 151 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 152 static int __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 153 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 154 static void __wdccommand_kill_xfer(struct ata_channel *, 155 struct ata_xfer *, int); 156 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 157 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 158 static int __wdcwait(struct ata_channel *, int, int, int, int *); 159 160 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 161 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 162 #define DEBUG_INTR 0x01 163 #define DEBUG_XFERS 0x02 164 #define DEBUG_STATUS 0x04 165 #define DEBUG_FUNCS 0x08 166 #define DEBUG_PROBE 0x10 167 #define DEBUG_DETACH 0x20 168 #define DEBUG_DELAY 0x40 169 #ifdef ATADEBUG 170 extern int atadebug_mask; /* init'ed in ata.c */ 171 int wdc_nxfer = 0; 172 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 173 #else 174 #define ATADEBUG_PRINT(args, level) 175 #endif 176 177 /* 178 * Initialize the "shadow register" handles for a standard wdc controller. 179 */ 180 void 181 wdc_init_shadow_regs(struct wdc_regs *wdr) 182 { 183 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 184 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 185 } 186 187 /* 188 * Allocate a wdc_regs array, based on the number of channels. 189 */ 190 void 191 wdc_allocate_regs(struct wdc_softc *wdc) 192 { 193 194 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 195 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 196 } 197 198 #if NSATA > 0 199 /* 200 * probe drives on SATA controllers with standard SATA registers: 201 * bring the PHYs online, read the drive signature and set drive flags 202 * appropriately. 203 */ 204 void 205 wdc_sataprobe(struct ata_channel *chp) 206 { 207 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 208 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 209 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 210 int i; 211 212 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 213 214 /* do this before we take lock */ 215 216 ata_channel_lock(chp); 217 218 /* reset the PHY and bring online */ 219 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 220 wdr->sata_status, AT_WAIT)) { 221 case SStatus_DET_DEV: 222 /* wait 5s for BSY to clear */ 223 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 224 bus_space_write_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 226 delay(10); /* 400ns delay */ 227 st = bus_space_read_1(wdr->cmd_iot, 228 wdr->cmd_iohs[wd_status], 0); 229 if ((st & WDCS_BSY) == 0) 230 break; 231 ata_delay(chp, 1, "sataprb", AT_WAIT); 232 } 233 if (i == WDC_PROBE_WAIT * hz) 234 aprint_error_dev(chp->ch_atac->atac_dev, 235 "BSY never cleared, status 0x%02x\n", st); 236 sc = bus_space_read_1(wdr->cmd_iot, 237 wdr->cmd_iohs[wd_seccnt], 0); 238 sn = bus_space_read_1(wdr->cmd_iot, 239 wdr->cmd_iohs[wd_sector], 0); 240 cl = bus_space_read_1(wdr->cmd_iot, 241 wdr->cmd_iohs[wd_cyl_lo], 0); 242 ch = bus_space_read_1(wdr->cmd_iot, 243 wdr->cmd_iohs[wd_cyl_hi], 0); 244 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 245 "cl=0x%x ch=0x%x\n", 246 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 247 sc, sn, cl, ch), DEBUG_PROBE); 248 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 249 ata_channel_unlock(chp); 250 return; 251 } 252 /* 253 * sc and sn are supposed to be 0x1 for ATAPI, but in some 254 * cases we get wrong values here, so ignore it. 255 */ 256 if (cl == 0x14 && ch == 0xeb) 257 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 258 else 259 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 260 261 /* 262 * issue a reset in case only the interface part of the drive 263 * is up 264 */ 265 if (wdcreset(chp, RESET_SLEEP) != 0) 266 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 267 break; 268 269 default: 270 break; 271 } 272 273 ata_channel_unlock(chp); 274 } 275 #endif /* NSATA > 0 */ 276 277 278 /* Test to see controller with at last one attached drive is there. 279 * Returns a bit for each possible drive found (0x01 for drive 0, 280 * 0x02 for drive 1). 281 * Logic: 282 * - If a status register is at 0xff, assume there is no drive here 283 * (ISA has pull-up resistors). Similarly if the status register has 284 * the value we last wrote to the bus (for IDE interfaces without pullups). 285 * If no drive at all -> return. 286 * - reset the controller, wait for it to complete (may take up to 31s !). 287 * If timeout -> return. 288 * - test ATA/ATAPI signatures. If at last one drive found -> return. 289 * - try an ATA command on the master. 290 */ 291 292 void 293 wdc_drvprobe(struct ata_channel *chp) 294 { 295 struct ataparams params; /* XXX: large struct */ 296 struct atac_softc *atac = chp->ch_atac; 297 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 298 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 299 u_int8_t st0 = 0, st1 = 0; 300 int i, j, error, tfd; 301 302 ata_channel_lock(chp); 303 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) { 304 ata_channel_unlock(chp); 305 return; 306 } 307 if (wdcprobe1(chp, 0) == 0) { 308 /* No drives, abort the attach here. */ 309 atabus_free_drives(chp); 310 ata_channel_unlock(chp); 311 return; 312 } 313 314 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 315 for (i = 0; i < mstohz(3000); i++) { 316 /* 317 * select drive 1 first, so that master is selected on 318 * exit from the loop 319 */ 320 if (chp->ch_ndrives > 1 && 321 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 322 if (wdc->select) 323 wdc->select(chp,1); 324 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 325 0, WDSD_IBM | 0x10); 326 delay(10); /* 400ns delay */ 327 st1 = bus_space_read_1(wdr->cmd_iot, 328 wdr->cmd_iohs[wd_status], 0); 329 } 330 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 331 if (wdc->select) 332 wdc->select(chp,0); 333 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 334 0, WDSD_IBM); 335 delay(10); /* 400ns delay */ 336 st0 = bus_space_read_1(wdr->cmd_iot, 337 wdr->cmd_iohs[wd_status], 0); 338 } 339 340 341 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 342 (st0 & WDCS_DRDY)) && 343 (chp->ch_ndrives < 2 || 344 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 345 (st1 & WDCS_DRDY))) 346 break; 347 #ifdef WDC_NO_IDS 348 /* cannot kpause here (can't enable IPL_BIO interrupts), 349 * delay instead 350 */ 351 delay(1000000 / hz); 352 #else 353 ata_delay(chp, 1, "atadrdy", AT_WAIT); 354 #endif 355 } 356 if ((st0 & WDCS_DRDY) == 0 && 357 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 358 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 359 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 360 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 361 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 362 ata_channel_unlock(chp); 363 364 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 365 device_xname(atac->atac_dev), 366 chp->ch_channel, st0, st1), DEBUG_PROBE); 367 368 /* Wait a bit, some devices are weird just after a reset. */ 369 delay(5000); 370 371 for (i = 0; i < chp->ch_ndrives; i++) { 372 #if NATA_DMA 373 /* 374 * Init error counter so that an error within the first xfers 375 * will trigger a downgrade 376 */ 377 chp->ch_drive[i].n_dmaerrs = NERRS_MAX - 1; 378 #endif 379 380 /* If controller can't do 16bit flag the drives as 32bit */ 381 if ((atac->atac_cap & 382 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 383 ata_channel_lock(chp); 384 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 385 ata_channel_unlock(chp); 386 } 387 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 388 continue; 389 390 /* Shortcut in case we've been shutdown */ 391 if (chp->ch_flags & ATACH_SHUTDOWN) 392 return; 393 394 /* 395 * Issue an identify, to try to detect ghosts. 396 * Note that we can't use interrupts here, because if there 397 * is no devices, we will get a command aborted without 398 * interrupts. 399 */ 400 error = ata_get_params(&chp->ch_drive[i], 401 AT_WAIT | AT_POLL, ¶ms); 402 if (error != CMD_OK) { 403 ata_channel_lock(chp); 404 ata_delay(chp, 1000, "atacnf", AT_WAIT); 405 ata_channel_unlock(chp); 406 407 /* Shortcut in case we've been shutdown */ 408 if (chp->ch_flags & ATACH_SHUTDOWN) 409 return; 410 411 error = ata_get_params(&chp->ch_drive[i], 412 AT_WAIT | AT_POLL, ¶ms); 413 } 414 if (error != CMD_OK) { 415 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 416 device_xname(atac->atac_dev), 417 chp->ch_channel, i, error), DEBUG_PROBE); 418 ata_channel_lock(chp); 419 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 420 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 421 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 422 ata_channel_unlock(chp); 423 continue; 424 } 425 /* 426 * Pre-ATA drive ? 427 * Test registers writability (Error register not 428 * writable, but cyllo is), then try an ATA command. 429 */ 430 if (wdc->select) 431 wdc->select(chp,i); 432 bus_space_write_1(wdr->cmd_iot, 433 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 434 delay(10); /* 400ns delay */ 435 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 436 0, 0x58); 437 bus_space_write_1(wdr->cmd_iot, 438 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 439 if (bus_space_read_1(wdr->cmd_iot, 440 wdr->cmd_iohs[wd_error], 0) == 0x58 || 441 bus_space_read_1(wdr->cmd_iot, 442 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 443 ATADEBUG_PRINT(("%s:%d:%d: register " 444 "writability failed\n", 445 device_xname(atac->atac_dev), 446 chp->ch_channel, i), DEBUG_PROBE); 447 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 448 ata_channel_unlock(chp); 449 continue; 450 } 451 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 452 WDCWAIT_TOUT) { 453 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 454 device_xname(atac->atac_dev), 455 chp->ch_channel, i), DEBUG_PROBE); 456 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 457 ata_channel_unlock(chp); 458 continue; 459 } 460 bus_space_write_1(wdr->cmd_iot, 461 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 462 delay(10); /* 400ns delay */ 463 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 464 WDCWAIT_TOUT) { 465 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 466 device_xname(atac->atac_dev), 467 chp->ch_channel, i), DEBUG_PROBE); 468 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 469 ata_channel_unlock(chp); 470 } else { 471 for (j = 0; j < chp->ch_ndrives; j++) { 472 if (chp->ch_drive[i].drive_type != 473 ATA_DRIVET_NONE) { 474 chp->ch_drive[j].drive_type = 475 ATA_DRIVET_OLD; 476 } 477 } 478 ata_channel_unlock(chp); 479 } 480 } 481 } 482 } 483 484 int 485 wdcprobe(struct wdc_regs *wdr) 486 { 487 488 return wdcprobe_with_reset(wdr, NULL); 489 } 490 491 int 492 wdcprobe_with_reset(struct wdc_regs *wdr, 493 void (*do_reset)(struct ata_channel *, int)) 494 { 495 struct wdc_softc *wdc; 496 struct ata_channel *ch; 497 int rv; 498 499 wdc = kmem_zalloc(sizeof(*wdc), KM_SLEEP); 500 ch = kmem_zalloc(sizeof(*ch), KM_SLEEP); 501 502 ata_channel_init(ch); 503 ch->ch_atac = &wdc->sc_atac; 504 wdc->regs = wdr; 505 506 /* check the MD reset method */ 507 wdc->reset = (do_reset != NULL) ? do_reset : wdc_do_reset; 508 509 ata_channel_lock(ch); 510 rv = wdcprobe1(ch, 1); 511 ata_channel_unlock(ch); 512 513 ata_channel_destroy(ch); 514 515 kmem_free(ch, sizeof(*ch)); 516 kmem_free(wdc, sizeof(*wdc)); 517 518 return rv; 519 } 520 521 static int 522 wdcprobe1(struct ata_channel *chp, int poll) 523 { 524 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 525 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 526 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 527 u_int8_t ret_value = 0x03; 528 u_int8_t drive; 529 /* XXX if poll, wdc_probe_count is 0. */ 530 int wdc_probe_count = 531 poll ? (WDC_PROBE_WAIT / WDCDELAY) 532 : (WDC_PROBE_WAIT * hz); 533 534 /* 535 * Sanity check to see if the wdc channel responds at all. 536 */ 537 538 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 539 while (wdc_probe_count-- > 0) { 540 if (wdc->select) 541 wdc->select(chp,0); 542 543 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 544 0, WDSD_IBM); 545 delay(10); /* 400ns delay */ 546 st0 = bus_space_read_1(wdr->cmd_iot, 547 wdr->cmd_iohs[wd_status], 0); 548 549 if (wdc->select) 550 wdc->select(chp,1); 551 552 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 553 0, WDSD_IBM | 0x10); 554 delay(10); /* 400ns delay */ 555 st1 = bus_space_read_1(wdr->cmd_iot, 556 wdr->cmd_iohs[wd_status], 0); 557 if ((st0 & WDCS_BSY) == 0) 558 break; 559 } 560 561 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 562 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 563 564 /* 565 * Is a drive present? Originally this code tested either 566 * for 0xff (ISA controller with no drive present; pull-ups 567 * take reg values high) or "echo", which meant writing to 568 * the notionally read-only geometry regs and seeing if we 569 * could read back what we wrote (if a drive is there, we 570 * will not). But some PCI controllers don't have the 571 * 0xff behavior and also share regs internally in a way 572 * that tricks the echo test, resulting in a 3 second delay 573 * later before we find no drive. We conditionally check for 574 * 0x00 which should catch this case because a drive that's 575 * actually present should have at least BSY or DRDY set. 576 */ 577 if (st0 == 0xff || st0 == WDSD_IBM) 578 ret_value &= ~0x01; 579 else if (st0 == 0x00 && 580 (wdc->cap & WDC_CAPABILITY_ZERO_ABSENT)) 581 ret_value &= ~0x01; 582 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 583 ret_value &= ~0x02; 584 else if (st0 == 0x00 && 585 (wdc->cap & WDC_CAPABILITY_ZERO_ABSENT)) 586 ret_value &= ~0x02; 587 /* Register writability test, drive 0. */ 588 if (ret_value & 0x01) { 589 if (wdc->select) 590 wdc->select(chp,0); 591 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 592 0, WDSD_IBM); 593 bus_space_write_1(wdr->cmd_iot, 594 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 595 cl = bus_space_read_1(wdr->cmd_iot, 596 wdr->cmd_iohs[wd_cyl_lo], 0); 597 if (cl != 0x02) { 598 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 599 "got 0x%x != 0x02\n", 600 __func__, chp->ch_channel, cl), 601 DEBUG_PROBE); 602 ret_value &= ~0x01; 603 } 604 bus_space_write_1(wdr->cmd_iot, 605 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 606 cl = bus_space_read_1(wdr->cmd_iot, 607 wdr->cmd_iohs[wd_cyl_lo], 0); 608 if (cl != 0x01) { 609 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 610 "got 0x%x != 0x01\n", 611 __func__, chp->ch_channel, cl), 612 DEBUG_PROBE); 613 ret_value &= ~0x01; 614 } 615 bus_space_write_1(wdr->cmd_iot, 616 wdr->cmd_iohs[wd_sector], 0, 0x01); 617 cl = bus_space_read_1(wdr->cmd_iot, 618 wdr->cmd_iohs[wd_sector], 0); 619 if (cl != 0x01) { 620 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 621 "got 0x%x != 0x01\n", 622 __func__, chp->ch_channel, cl), 623 DEBUG_PROBE); 624 ret_value &= ~0x01; 625 } 626 bus_space_write_1(wdr->cmd_iot, 627 wdr->cmd_iohs[wd_sector], 0, 0x02); 628 cl = bus_space_read_1(wdr->cmd_iot, 629 wdr->cmd_iohs[wd_sector], 0); 630 if (cl != 0x02) { 631 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 632 "got 0x%x != 0x02\n", 633 __func__, chp->ch_channel, cl), 634 DEBUG_PROBE); 635 ret_value &= ~0x01; 636 } 637 cl = bus_space_read_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_cyl_lo], 0); 639 if (cl != 0x01) { 640 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 641 "got 0x%x != 0x01\n", 642 __func__, chp->ch_channel, cl), 643 DEBUG_PROBE); 644 ret_value &= ~0x01; 645 } 646 } 647 /* Register writability test, drive 1. */ 648 if (ret_value & 0x02) { 649 if (wdc->select) 650 wdc->select(chp,1); 651 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 652 0, WDSD_IBM | 0x10); 653 bus_space_write_1(wdr->cmd_iot, 654 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 655 cl = bus_space_read_1(wdr->cmd_iot, 656 wdr->cmd_iohs[wd_cyl_lo], 0); 657 if (cl != 0x02) { 658 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 659 "got 0x%x != 0x02\n", 660 __func__, chp->ch_channel, cl), 661 DEBUG_PROBE); 662 ret_value &= ~0x02; 663 } 664 bus_space_write_1(wdr->cmd_iot, 665 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 666 cl = bus_space_read_1(wdr->cmd_iot, 667 wdr->cmd_iohs[wd_cyl_lo], 0); 668 if (cl != 0x01) { 669 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 670 "got 0x%x != 0x01\n", 671 __func__, chp->ch_channel, cl), 672 DEBUG_PROBE); 673 ret_value &= ~0x02; 674 } 675 bus_space_write_1(wdr->cmd_iot, 676 wdr->cmd_iohs[wd_sector], 0, 0x01); 677 cl = bus_space_read_1(wdr->cmd_iot, 678 wdr->cmd_iohs[wd_sector], 0); 679 if (cl != 0x01) { 680 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 681 "got 0x%x != 0x01\n", 682 __func__, chp->ch_channel, cl), 683 DEBUG_PROBE); 684 ret_value &= ~0x02; 685 } 686 bus_space_write_1(wdr->cmd_iot, 687 wdr->cmd_iohs[wd_sector], 0, 0x02); 688 cl = bus_space_read_1(wdr->cmd_iot, 689 wdr->cmd_iohs[wd_sector], 0); 690 if (cl != 0x02) { 691 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 692 "got 0x%x != 0x02\n", 693 __func__, chp->ch_channel, cl), 694 DEBUG_PROBE); 695 ret_value &= ~0x02; 696 } 697 cl = bus_space_read_1(wdr->cmd_iot, 698 wdr->cmd_iohs[wd_cyl_lo], 0); 699 if (cl != 0x01) { 700 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 701 "got 0x%x != 0x01\n", 702 __func__, chp->ch_channel, cl), 703 DEBUG_PROBE); 704 ret_value &= ~0x02; 705 } 706 } 707 708 if (ret_value == 0) { 709 return 0; 710 } 711 } 712 713 #if 0 /* XXX this break some ATA or ATAPI devices */ 714 /* 715 * reset bus. Also send an ATAPI_RESET to devices, in case there are 716 * ATAPI device out there which don't react to the bus reset 717 */ 718 if (ret_value & 0x01) { 719 if (wdc->select) 720 wdc->select(chp,0); 721 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 722 0, WDSD_IBM); 723 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 724 ATAPI_SOFT_RESET); 725 } 726 if (ret_value & 0x02) { 727 if (wdc->select) 728 wdc->select(chp,0); 729 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 730 0, WDSD_IBM | 0x10); 731 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 732 ATAPI_SOFT_RESET); 733 } 734 735 delay(5000); 736 #endif 737 738 wdc->reset(chp, RESET_POLL); 739 DELAY(2000); 740 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 741 742 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 743 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 744 WDCTL_4BIT); 745 746 #ifdef WDC_NO_IDS 747 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 748 #else 749 ret_value = __wdcwait_reset(chp, ret_value, poll); 750 #endif 751 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 752 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 753 754 /* if reset failed, there's nothing here */ 755 if (ret_value == 0) { 756 return 0; 757 } 758 759 /* 760 * Test presence of drives. First test register signatures looking 761 * for ATAPI devices. If it's not an ATAPI and reset said there may 762 * be something here assume it's ATA or OLD. Ghost will be killed 763 * later in attach routine. 764 */ 765 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 766 if ((ret_value & (0x01 << drive)) == 0) 767 continue; 768 if (wdc->select) 769 wdc->select(chp,drive); 770 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 771 WDSD_IBM | (drive << 4)); 772 delay(10); /* 400ns delay */ 773 /* Save registers contents */ 774 sc = bus_space_read_1(wdr->cmd_iot, 775 wdr->cmd_iohs[wd_seccnt], 0); 776 sn = bus_space_read_1(wdr->cmd_iot, 777 wdr->cmd_iohs[wd_sector], 0); 778 cl = bus_space_read_1(wdr->cmd_iot, 779 wdr->cmd_iohs[wd_cyl_lo], 0); 780 ch = bus_space_read_1(wdr->cmd_iot, 781 wdr->cmd_iohs[wd_cyl_hi], 0); 782 783 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 784 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 785 sn, cl, ch), DEBUG_PROBE); 786 /* 787 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 788 * we get wrong values here, so ignore it. 789 */ 790 if (chp->ch_drive != NULL) { 791 if (cl == 0x14 && ch == 0xeb) { 792 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 793 } else { 794 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 795 } 796 } 797 } 798 /* 799 * Select an existing drive before lowering spl, some WDC_NO_IDS 800 * devices incorrectly assert IRQ on nonexistent slave 801 */ 802 if (ret_value & 0x01) { 803 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 804 WDSD_IBM); 805 (void)bus_space_read_1(wdr->cmd_iot, 806 wdr->cmd_iohs[wd_status], 0); 807 } 808 return (ret_value); 809 } 810 811 void 812 wdcattach(struct ata_channel *chp) 813 { 814 struct atac_softc *atac = chp->ch_atac; 815 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 816 817 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 818 819 /* default data transfer methods */ 820 if (wdc->datain_pio == NULL) 821 wdc->datain_pio = wdc_datain_pio; 822 if (wdc->dataout_pio == NULL) 823 wdc->dataout_pio = wdc_dataout_pio; 824 /* default reset method */ 825 if (wdc->reset == NULL) 826 wdc->reset = wdc_do_reset; 827 828 /* initialise global data */ 829 if (atac->atac_bustype_ata == NULL) 830 atac->atac_bustype_ata = &wdc_ata_bustype; 831 if (atac->atac_probe == NULL) 832 atac->atac_probe = wdc_drvprobe; 833 #if NATAPIBUS > 0 834 if (atac->atac_atapibus_attach == NULL) 835 atac->atac_atapibus_attach = wdc_atapibus_attach; 836 #endif 837 838 ata_channel_attach(chp); 839 } 840 841 void 842 wdc_childdetached(device_t self, device_t child) 843 { 844 struct atac_softc *atac = device_private(self); 845 struct ata_channel *chp; 846 int i; 847 848 for (i = 0; i < atac->atac_nchannels; i++) { 849 chp = atac->atac_channels[i]; 850 if (child == chp->atabus) { 851 chp->atabus = NULL; 852 return; 853 } 854 } 855 } 856 857 int 858 wdcdetach(device_t self, int flags) 859 { 860 struct atac_softc *atac = device_private(self); 861 struct ata_channel *chp; 862 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 863 int i, error = 0; 864 865 for (i = 0; i < atac->atac_nchannels; i++) { 866 chp = atac->atac_channels[i]; 867 if (chp->atabus == NULL) 868 continue; 869 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 870 device_xname(atac->atac_dev), device_xname(chp->atabus)), 871 DEBUG_DETACH); 872 if ((error = config_detach(chp->atabus, flags)) != 0) 873 return error; 874 ata_channel_detach(chp); 875 } 876 if (adapt->adapt_refcnt != 0) 877 return EBUSY; 878 return 0; 879 } 880 881 /* restart an interrupted I/O */ 882 void 883 wdcrestart(void *v) 884 { 885 struct ata_channel *chp = v; 886 int s; 887 888 s = splbio(); 889 atastart(chp); 890 splx(s); 891 } 892 893 894 /* 895 * Interrupt routine for the controller. Acknowledge the interrupt, check for 896 * errors on the current operation, mark it done if necessary, and start the 897 * next request. Also check for a partially done transfer, and continue with 898 * the next chunk if so. 899 */ 900 int 901 wdcintr(void *arg) 902 { 903 struct ata_channel *chp = arg; 904 struct atac_softc *atac = chp->ch_atac; 905 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 906 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 907 struct ata_xfer *xfer; 908 int ret; 909 910 if (!device_is_active(atac->atac_dev)) { 911 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 912 DEBUG_INTR); 913 return (0); 914 } 915 916 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) 917 goto ignore; 918 919 xfer = ata_queue_get_active_xfer(chp); 920 if (xfer == NULL) { 921 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 922 ignore: 923 /* try to clear the pending interrupt anyway */ 924 (void)bus_space_read_1(wdr->cmd_iot, 925 wdr->cmd_iohs[wd_status], 0); 926 return (0); 927 } 928 929 /* 930 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 931 * actually has no effect, and interrupt is triggered regardless. 932 * Ignore polled commands here, they are processed separately. 933 */ 934 if (ISSET(xfer->c_flags, C_POLL)) { 935 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 936 DEBUG_INTR); 937 goto ignore; 938 } 939 940 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 941 KASSERT(xfer != NULL); 942 943 #if NATA_DMA || NATA_PIOBM 944 if (chp->ch_flags & ATACH_DMA_WAIT) { 945 wdc->dma_status = 946 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 947 xfer->c_drive, WDC_DMAEND_END); 948 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 949 /* IRQ not for us, not detected by DMA engine */ 950 return 0; 951 } 952 chp->ch_flags &= ~ATACH_DMA_WAIT; 953 } 954 #endif 955 chp->ch_flags &= ~ATACH_IRQ_WAIT; 956 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 957 ret = xfer->ops->c_intr(chp, xfer, 1); 958 if (ret == 0) /* irq was not for us, still waiting for irq */ 959 chp->ch_flags |= ATACH_IRQ_WAIT; 960 return (ret); 961 } 962 963 /* Put all disk in RESET state */ 964 void 965 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 966 { 967 struct ata_channel *chp = drvp->chnl_softc; 968 969 ata_channel_lock_owned(chp); 970 971 KASSERT(sigp == NULL); 972 973 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 974 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 975 drvp->drive), DEBUG_FUNCS); 976 977 ata_thread_run(chp, flags, ATACH_TH_RESET, ATACH_NODRIVE); 978 } 979 980 void 981 wdc_reset_channel(struct ata_channel *chp, int flags) 982 { 983 struct ata_xfer *xfer; 984 985 ata_channel_lock_owned(chp); 986 987 #if NATA_DMA || NATA_PIOBM 988 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 989 #endif 990 991 chp->ch_flags &= ~ATACH_IRQ_WAIT; 992 993 /* 994 * if the current command is on an ATAPI device, issue a 995 * ATAPI_SOFT_RESET 996 */ 997 xfer = ata_queue_get_active_xfer_locked(chp); 998 999 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 1000 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1001 ata_delay(chp, 1000, "atardl", flags); 1002 } 1003 1004 /* reset the channel */ 1005 if (flags & AT_WAIT) 1006 (void) wdcreset(chp, RESET_SLEEP); 1007 else 1008 (void) wdcreset(chp, RESET_POLL); 1009 1010 /* 1011 * wait a bit after reset; in case the DMA engines needs some time 1012 * to recover. 1013 */ 1014 ata_delay(chp, 1000, "atardl", flags); 1015 1016 /* 1017 * Look for pending xfers. If we have a shared queue, we'll also reset 1018 * the other channel if the current xfer is running on it. 1019 * Then we'll kill the eventual active transfer explicitly, so that 1020 * it is queued for retry immediately without waiting for I/O timeout. 1021 */ 1022 if (xfer) { 1023 if (xfer->c_chp != chp) { 1024 ata_thread_run(xfer->c_chp, flags, ATACH_TH_RESET, 1025 ATACH_NODRIVE); 1026 } else { 1027 #if NATA_DMA || NATA_PIOBM 1028 /* 1029 * If we're waiting for DMA, stop the 1030 * DMA engine 1031 */ 1032 if (chp->ch_flags & ATACH_DMA_WAIT) { 1033 (*wdc->dma_finish)(wdc->dma_arg, 1034 chp->ch_channel, xfer->c_drive, 1035 WDC_DMAEND_ABRT_QUIET); 1036 chp->ch_flags &= ~ATACH_DMA_WAIT; 1037 } 1038 #endif 1039 } 1040 } 1041 1042 ata_kill_active(chp, KILL_RESET, flags); 1043 } 1044 1045 static int 1046 wdcreset(struct ata_channel *chp, int poll) 1047 { 1048 struct atac_softc *atac = chp->ch_atac; 1049 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1050 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1051 int drv_mask1 = 0, drv_mask2; 1052 1053 ata_channel_lock_owned(chp); 1054 1055 #ifdef WDC_NO_IDS 1056 poll = RESET_POLL; 1057 #endif 1058 wdc->reset(chp, poll); 1059 1060 if (chp->ch_ndrives > 0) 1061 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1062 ? 0x01 : 0x00; 1063 if (chp->ch_ndrives > 1) 1064 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1065 ? 0x02 : 0x00; 1066 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1067 (poll == RESET_SLEEP) ? 0 : 1); 1068 if (drv_mask2 != drv_mask1) { 1069 aprint_error("%s channel %d: reset failed for", 1070 device_xname(atac->atac_dev), chp->ch_channel); 1071 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1072 aprint_normal(" drive 0"); 1073 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1074 aprint_normal(" drive 1"); 1075 aprint_normal("\n"); 1076 } 1077 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1078 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1079 WDCTL_4BIT); 1080 1081 return (drv_mask1 != drv_mask2) ? 1 : 0; 1082 } 1083 1084 void 1085 wdc_do_reset(struct ata_channel *chp, int poll) 1086 { 1087 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1088 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1089 int s = 0; 1090 1091 if (poll != RESET_SLEEP) 1092 s = splbio(); 1093 if (wdc->select) 1094 wdc->select(chp,0); 1095 /* master */ 1096 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1097 delay(10); /* 400ns delay */ 1098 /* assert SRST, wait for reset to complete */ 1099 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1100 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1101 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1102 delay(2000); 1103 } 1104 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1105 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1106 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1107 WDCTL_4BIT | WDCTL_IDS); 1108 delay(10); /* 400ns delay */ 1109 if (poll != RESET_SLEEP) { 1110 /* ACK interrupt in case there is one pending left */ 1111 if (wdc->irqack) 1112 wdc->irqack(chp); 1113 splx(s); 1114 } 1115 } 1116 1117 static int 1118 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1119 { 1120 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1121 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1122 int timeout, nloop; 1123 int wflags = poll ? AT_POLL : AT_WAIT; 1124 u_int8_t st0 = 0, st1 = 0; 1125 #ifdef ATADEBUG 1126 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1127 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1128 #endif 1129 if (poll) 1130 nloop = WDCNDELAY_RST; 1131 else 1132 nloop = WDC_RESET_WAIT * hz / 1000; 1133 /* wait for BSY to deassert */ 1134 for (timeout = 0; timeout < nloop; timeout++) { 1135 if ((drv_mask & 0x01) != 0) { 1136 if (wdc->select) 1137 wdc->select(chp,0); 1138 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1139 0, WDSD_IBM); /* master */ 1140 delay(10); 1141 st0 = bus_space_read_1(wdr->cmd_iot, 1142 wdr->cmd_iohs[wd_status], 0); 1143 #ifdef ATADEBUG 1144 sc0 = bus_space_read_1(wdr->cmd_iot, 1145 wdr->cmd_iohs[wd_seccnt], 0); 1146 sn0 = bus_space_read_1(wdr->cmd_iot, 1147 wdr->cmd_iohs[wd_sector], 0); 1148 cl0 = bus_space_read_1(wdr->cmd_iot, 1149 wdr->cmd_iohs[wd_cyl_lo], 0); 1150 ch0 = bus_space_read_1(wdr->cmd_iot, 1151 wdr->cmd_iohs[wd_cyl_hi], 0); 1152 #endif 1153 } 1154 if ((drv_mask & 0x02) != 0) { 1155 if (wdc->select) 1156 wdc->select(chp,1); 1157 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1158 0, WDSD_IBM | 0x10); /* slave */ 1159 delay(10); 1160 st1 = bus_space_read_1(wdr->cmd_iot, 1161 wdr->cmd_iohs[wd_status], 0); 1162 #ifdef ATADEBUG 1163 sc1 = bus_space_read_1(wdr->cmd_iot, 1164 wdr->cmd_iohs[wd_seccnt], 0); 1165 sn1 = bus_space_read_1(wdr->cmd_iot, 1166 wdr->cmd_iohs[wd_sector], 0); 1167 cl1 = bus_space_read_1(wdr->cmd_iot, 1168 wdr->cmd_iohs[wd_cyl_lo], 0); 1169 ch1 = bus_space_read_1(wdr->cmd_iot, 1170 wdr->cmd_iohs[wd_cyl_hi], 0); 1171 #endif 1172 } 1173 1174 if ((drv_mask & 0x01) == 0) { 1175 /* no master */ 1176 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1177 /* No master, slave is ready, it's done */ 1178 goto end; 1179 } 1180 if ((drv_mask & 0x02) == 0) { 1181 /* No master, no slave: it's done */ 1182 goto end; 1183 } 1184 } else if ((drv_mask & 0x02) == 0) { 1185 /* no slave */ 1186 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1187 /* No slave, master is ready, it's done */ 1188 goto end; 1189 } 1190 } else { 1191 /* Wait for both master and slave to be ready */ 1192 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1193 goto end; 1194 } 1195 } 1196 ata_delay(chp, WDCDELAY, "atarst", wflags); 1197 } 1198 /* Reset timed out. Maybe it's because drv_mask was not right */ 1199 if (st0 & WDCS_BSY) 1200 drv_mask &= ~0x01; 1201 if (st1 & WDCS_BSY) 1202 drv_mask &= ~0x02; 1203 end: 1204 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1205 "cl=0x%x ch=0x%x\n", 1206 device_xname(chp->ch_atac->atac_dev), 1207 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1208 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1209 "cl=0x%x ch=0x%x\n", 1210 device_xname(chp->ch_atac->atac_dev), 1211 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1212 1213 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1214 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1215 st0, st1), DEBUG_PROBE); 1216 1217 return drv_mask; 1218 } 1219 1220 /* 1221 * Wait for a drive to be !BSY, and have mask in its status register. 1222 * return -1 for a timeout after "timeout" ms. 1223 */ 1224 static int 1225 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1226 { 1227 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1228 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1229 u_char status, error = 0; 1230 int xtime = 0; 1231 int rv; 1232 1233 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1234 device_xname(chp->ch_atac->atac_dev), 1235 chp->ch_channel), DEBUG_STATUS); 1236 *tfd = 0; 1237 1238 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1239 1240 for (;;) { 1241 status = 1242 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1243 if ((status & (WDCS_BSY | mask)) == bits) 1244 break; 1245 if (++xtime > timeout) { 1246 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1247 "status %x error %x (mask 0x%x bits 0x%x)\n", 1248 xtime, status, 1249 bus_space_read_1(wdr->cmd_iot, 1250 wdr->cmd_iohs[wd_error], 0), mask, bits), 1251 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1252 rv = WDCWAIT_TOUT; 1253 goto out; 1254 } 1255 delay(WDCDELAY); 1256 } 1257 #ifdef ATADEBUG 1258 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1259 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1260 #endif 1261 if (status & WDCS_ERR) 1262 error = bus_space_read_1(wdr->cmd_iot, 1263 wdr->cmd_iohs[wd_error], 0); 1264 #ifdef WDCNDELAY_DEBUG 1265 /* After autoconfig, there should be no long delays. */ 1266 if (!cold && xtime > WDCNDELAY_DEBUG) { 1267 struct ata_xfer *xfer; 1268 1269 xfer = ata_queue_get_active_xfer_locked(chp); 1270 if (xfer == NULL) 1271 printf("%s channel %d: warning: busy-wait took %dus\n", 1272 device_xname(chp->ch_atac->atac_dev), 1273 chp->ch_channel, WDCDELAY * xtime); 1274 else 1275 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1276 device_xname(chp->ch_atac->atac_dev), 1277 chp->ch_channel, xfer->c_drive, 1278 WDCDELAY * xtime); 1279 } 1280 #endif 1281 rv = WDCWAIT_OK; 1282 1283 out: 1284 *tfd = ATACH_ERR_ST(error, status); 1285 return rv; 1286 } 1287 1288 /* 1289 * Call __wdcwait(), polling using kpause() or waking up the kernel 1290 * thread if possible 1291 */ 1292 int 1293 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1294 int *tfd) 1295 { 1296 int error, i, timeout_hz = mstohz(timeout); 1297 1298 ata_channel_lock_owned(chp); 1299 1300 if (timeout_hz == 0 || 1301 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1302 error = __wdcwait(chp, mask, bits, timeout, tfd); 1303 else { 1304 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1305 if (error != 0) { 1306 if (ata_is_thread_run(chp) || (flags & AT_WAIT)) { 1307 /* 1308 * we're running in the channel thread 1309 * or some userland thread context 1310 */ 1311 for (i = 0; i < timeout_hz; i++) { 1312 if (__wdcwait(chp, mask, bits, 1313 WDCDELAY_POLL, tfd) == 0) { 1314 error = 0; 1315 break; 1316 } 1317 kpause("atapoll", true, 1, 1318 &chp->ch_lock); 1319 } 1320 } else { 1321 /* 1322 * we're probably in interrupt context, 1323 * caller must ask the thread to come back here 1324 */ 1325 return(WDCWAIT_THR); 1326 } 1327 } 1328 } 1329 return (error); 1330 } 1331 1332 1333 #if NATA_DMA 1334 /* 1335 * Busy-wait for DMA to complete 1336 */ 1337 int 1338 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1339 { 1340 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1341 int xtime; 1342 1343 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1344 wdc->dma_status = 1345 (*wdc->dma_finish)(wdc->dma_arg, 1346 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1347 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1348 return 0; 1349 delay(WDCDELAY); 1350 } 1351 /* timeout, force a DMA halt */ 1352 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1353 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1354 return 1; 1355 } 1356 #endif 1357 1358 void 1359 wdctimeout(void *arg) 1360 { 1361 struct ata_xfer *xfer; 1362 struct ata_channel *chp = arg; 1363 #if NATA_DMA || NATA_PIOBM 1364 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1365 #endif 1366 int s; 1367 1368 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1369 1370 s = splbio(); 1371 1372 callout_ack(&chp->c_timo_callout); 1373 1374 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 1375 __wdcerror(chp, "timeout not expected without pending irq"); 1376 goto out; 1377 } 1378 1379 xfer = ata_queue_get_active_xfer(chp); 1380 KASSERT(xfer != NULL); 1381 1382 if (ata_timo_xfer_check(xfer)) { 1383 /* Already logged */ 1384 goto out; 1385 } 1386 1387 __wdcerror(chp, "lost interrupt"); 1388 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1389 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1390 xfer->c_bcount, xfer->c_skip); 1391 #if NATA_DMA || NATA_PIOBM 1392 if (chp->ch_flags & ATACH_DMA_WAIT) { 1393 wdc->dma_status = 1394 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1395 xfer->c_drive, WDC_DMAEND_ABRT); 1396 chp->ch_flags &= ~ATACH_DMA_WAIT; 1397 } 1398 #endif 1399 /* 1400 * Call the interrupt routine. If we just missed an interrupt, 1401 * it will do what's needed. Else, it will take the needed 1402 * action (reset the device). 1403 */ 1404 xfer->c_flags |= C_TIMEOU; 1405 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1406 KASSERT(xfer->ops != NULL && xfer->ops->c_intr != NULL); 1407 xfer->ops->c_intr(chp, xfer, 1); 1408 1409 out: 1410 splx(s); 1411 } 1412 1413 static const struct ata_xfer_ops wdc_cmd_xfer_ops = { 1414 .c_start = __wdccommand_start, 1415 .c_poll = __wdccommand_poll, 1416 .c_abort = __wdccommand_done, 1417 .c_intr = __wdccommand_intr, 1418 .c_kill_xfer = __wdccommand_kill_xfer, 1419 }; 1420 1421 void 1422 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1423 { 1424 struct ata_channel *chp = drvp->chnl_softc; 1425 struct ata_command *ata_c = &xfer->c_ata_c; 1426 1427 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1428 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1429 drvp->drive), DEBUG_FUNCS); 1430 1431 /* set up an xfer and queue. Wait for completion */ 1432 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1433 ata_c->flags |= AT_POLL; 1434 if (ata_c->flags & AT_POLL) 1435 xfer->c_flags |= C_POLL; 1436 if (ata_c->flags & AT_WAIT) 1437 xfer->c_flags |= C_WAIT; 1438 xfer->c_drive = drvp->drive; 1439 xfer->c_databuf = ata_c->data; 1440 xfer->c_bcount = ata_c->bcount; 1441 xfer->ops = &wdc_cmd_xfer_ops; 1442 1443 ata_exec_xfer(chp, xfer); 1444 } 1445 1446 static int 1447 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1448 { 1449 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1450 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1451 int drive = xfer->c_drive; 1452 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1453 struct ata_command *ata_c = &xfer->c_ata_c; 1454 int tfd; 1455 1456 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1457 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1458 xfer->c_drive), DEBUG_FUNCS); 1459 1460 if (wdc->select) 1461 wdc->select(chp,drive); 1462 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1463 WDSD_IBM | (drive << 4)); 1464 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1465 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1466 case WDCWAIT_OK: 1467 break; 1468 case WDCWAIT_TOUT: 1469 ata_c->flags |= AT_TIMEOU; 1470 return ATASTART_ABORT; 1471 case WDCWAIT_THR: 1472 return ATASTART_TH; 1473 } 1474 if (ata_c->flags & AT_POLL) { 1475 /* polled command, disable interrupts */ 1476 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1477 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1478 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1479 } 1480 if ((ata_c->flags & AT_LBA48) != 0) { 1481 wdccommandext(chp, drive, ata_c->r_command, 1482 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1483 ata_c->r_device & ~0x10); 1484 } else { 1485 wdccommand(chp, drive, ata_c->r_command, 1486 (ata_c->r_lba >> 8) & 0xffff, 1487 WDSD_IBM | (drive << 4) | 1488 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1489 ((ata_c->r_lba >> 24) & 0x0f), 1490 ata_c->r_lba & 0xff, 1491 ata_c->r_count & 0xff, 1492 ata_c->r_features & 0xff); 1493 } 1494 1495 if ((ata_c->flags & AT_POLL) == 0) { 1496 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1497 callout_reset(&chp->c_timo_callout, ata_c->timeout / 1000 * hz, 1498 wdctimeout, chp); 1499 return ATASTART_STARTED; 1500 } 1501 1502 /* 1503 * Polled command. Wait for drive ready or drq. Done in intr(). 1504 * Wait for at last 400ns for status bit to be valid. 1505 */ 1506 delay(10); /* 400ns delay */ 1507 return ATASTART_POLL; 1508 } 1509 1510 static int 1511 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1512 { 1513 __wdccommand_intr(chp, xfer, 0); 1514 return ATAPOLL_DONE; 1515 } 1516 1517 static int 1518 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1519 { 1520 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1521 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1522 struct ata_command *ata_c = &xfer->c_ata_c; 1523 int bcount = ata_c->bcount; 1524 char *data = ata_c->data; 1525 int wflags, tfd; 1526 int drive_flags; 1527 1528 if (ata_c->r_command == WDCC_IDENTIFY || 1529 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1530 /* 1531 * The IDENTIFY data has been designed as an array of 1532 * u_int16_t, so we can byteswap it on the fly. 1533 * Historically it's what we have always done so keeping it 1534 * here ensure binary backward compatibility. 1535 */ 1536 drive_flags = ATA_DRIVE_NOSTREAM | 1537 chp->ch_drive[xfer->c_drive].drive_flags; 1538 } else { 1539 /* 1540 * Other data structure are opaque and should be transferred 1541 * as is. 1542 */ 1543 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1544 } 1545 1546 #ifdef WDC_NO_IDS 1547 wflags = AT_POLL; 1548 #else 1549 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1550 /* both wait and poll, we can kpause here */ 1551 wflags = AT_WAIT | AT_POLL; 1552 } else { 1553 wflags = AT_POLL; 1554 } 1555 #endif 1556 1557 ata_channel_lock(chp); 1558 1559 again: 1560 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1561 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1562 xfer->c_drive), DEBUG_INTR); 1563 /* 1564 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1565 * Reselect again, it doesn't hurt for others commands, and the time 1566 * penalty for the extra register write is acceptable, 1567 * wdc_exec_command() isn't called often (mostly for autoconfig) 1568 */ 1569 if ((xfer->c_flags & C_ATAPI) != 0) { 1570 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1571 WDSD_IBM | (xfer->c_drive << 4)); 1572 } 1573 if ((ata_c->flags & AT_XFDONE) != 0) { 1574 /* 1575 * We have completed a data xfer. The drive should now be 1576 * in its initial state 1577 */ 1578 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1579 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1580 wflags, &tfd) == WDCWAIT_TOUT) { 1581 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1582 ata_channel_unlock(chp); 1583 return 0; /* IRQ was not for us */ 1584 } 1585 ata_c->flags |= AT_TIMEOU; 1586 } 1587 goto out; 1588 } 1589 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1590 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1591 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1592 ata_channel_unlock(chp); 1593 return 0; /* IRQ was not for us */ 1594 } 1595 ata_c->flags |= AT_TIMEOU; 1596 goto out; 1597 } 1598 if (wdc->irqack) 1599 wdc->irqack(chp); 1600 if (ata_c->flags & AT_READ) { 1601 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1602 ata_c->flags |= AT_TIMEOU; 1603 goto out; 1604 } 1605 wdc->datain_pio(chp, drive_flags, data, bcount); 1606 /* at this point the drive should be in its initial state */ 1607 ata_c->flags |= AT_XFDONE; 1608 /* 1609 * XXX checking the status register again here cause some 1610 * hardware to timeout. 1611 */ 1612 } else if (ata_c->flags & AT_WRITE) { 1613 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1614 ata_c->flags |= AT_TIMEOU; 1615 goto out; 1616 } 1617 wdc->dataout_pio(chp, drive_flags, data, bcount); 1618 ata_c->flags |= AT_XFDONE; 1619 if ((ata_c->flags & AT_POLL) == 0) { 1620 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1621 callout_reset(&chp->c_timo_callout, 1622 mstohz(ata_c->timeout), wdctimeout, chp); 1623 ata_channel_unlock(chp); 1624 return 1; 1625 } else { 1626 goto again; 1627 } 1628 } 1629 out: 1630 if (ATACH_ST(tfd) & WDCS_DWF) 1631 ata_c->flags |= AT_DF; 1632 if (ATACH_ST(tfd) & WDCS_ERR) { 1633 ata_c->flags |= AT_ERROR; 1634 ata_c->r_error = ATACH_ST(tfd); 1635 } 1636 1637 ata_channel_unlock(chp); 1638 1639 __wdccommand_done(chp, xfer); 1640 return 1; 1641 } 1642 1643 static void 1644 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1645 { 1646 struct atac_softc *atac = chp->ch_atac; 1647 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1648 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1649 struct ata_command *ata_c = &xfer->c_ata_c; 1650 bool start = true; 1651 1652 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1653 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1654 ata_c->flags), DEBUG_FUNCS); 1655 1656 if (ata_waitdrain_xfer_check(chp, xfer)) { 1657 start = false; 1658 goto out; 1659 } 1660 1661 if ((ata_c->flags & AT_READREG) != 0 && 1662 device_is_active(atac->atac_dev) && 1663 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1664 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1665 wdr->cmd_iohs[wd_status], 0); 1666 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1667 wdr->cmd_iohs[wd_error], 0); 1668 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1669 wdr->cmd_iohs[wd_seccnt], 0); 1670 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1671 wdr->cmd_iohs[wd_sector], 0) << 0; 1672 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1673 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1674 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1675 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1676 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1677 wdr->cmd_iohs[wd_sdh], 0); 1678 1679 if ((ata_c->flags & AT_LBA48) != 0) { 1680 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1681 if ((ata_c->flags & AT_POLL) != 0) 1682 bus_space_write_1(wdr->ctl_iot, 1683 wdr->ctl_ioh, wd_aux_ctlr, 1684 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1685 else 1686 bus_space_write_1(wdr->ctl_iot, 1687 wdr->ctl_ioh, wd_aux_ctlr, 1688 WDCTL_HOB|WDCTL_4BIT); 1689 } 1690 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1691 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1692 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1693 wdr->cmd_iohs[wd_sector], 0) << 24; 1694 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1695 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1696 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1697 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1698 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1699 if ((ata_c->flags & AT_POLL) != 0) 1700 bus_space_write_1(wdr->ctl_iot, 1701 wdr->ctl_ioh, wd_aux_ctlr, 1702 WDCTL_4BIT|WDCTL_IDS); 1703 else 1704 bus_space_write_1(wdr->ctl_iot, 1705 wdr->ctl_ioh, wd_aux_ctlr, 1706 WDCTL_4BIT); 1707 } 1708 } else { 1709 ata_c->r_lba |= 1710 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1711 } 1712 ata_c->r_device &= 0xf0; 1713 } 1714 1715 __wdccommand_done_end(chp, xfer); 1716 1717 ata_deactivate_xfer(chp, xfer); 1718 1719 out: 1720 if (ata_c->flags & AT_POLL) { 1721 /* enable interrupts */ 1722 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1723 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1724 wd_aux_ctlr, WDCTL_4BIT); 1725 delay(10); /* some drives need a little delay here */ 1726 } 1727 1728 if (start) 1729 atastart(chp); 1730 } 1731 1732 static void 1733 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1734 { 1735 struct ata_command *ata_c = &xfer->c_ata_c; 1736 1737 ata_c->flags |= AT_DONE; 1738 } 1739 1740 static void 1741 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1742 int reason) 1743 { 1744 struct ata_command *ata_c = &xfer->c_ata_c; 1745 bool deactivate = true; 1746 1747 switch (reason) { 1748 case KILL_GONE_INACTIVE: 1749 deactivate = false; 1750 /* FALLTHROUGH */ 1751 case KILL_GONE: 1752 ata_c->flags |= AT_GONE; 1753 break; 1754 case KILL_RESET: 1755 ata_c->flags |= AT_RESET; 1756 break; 1757 default: 1758 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1759 reason); 1760 panic("__wdccommand_kill_xfer"); 1761 } 1762 1763 __wdccommand_done_end(chp, xfer); 1764 1765 if (deactivate) 1766 ata_deactivate_xfer(chp, xfer); 1767 } 1768 1769 /* 1770 * Send a command. The drive should be ready. 1771 * Assumes interrupts are blocked. 1772 */ 1773 void 1774 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1775 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1776 u_int8_t features) 1777 { 1778 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1779 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1780 1781 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1782 "sector=%d count=%d features=%d\n", 1783 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1784 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1785 1786 if (wdc->select) 1787 wdc->select(chp,drive); 1788 1789 /* Select drive, head, and addressing mode. */ 1790 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1791 WDSD_IBM | (drive << 4) | head); 1792 /* Load parameters into the wd_features register. */ 1793 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1794 features); 1795 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1796 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1797 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1798 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1799 0, cylin >> 8); 1800 1801 /* Send command. */ 1802 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1803 return; 1804 } 1805 1806 /* 1807 * Send a 48-bit addressing command. The drive should be ready. 1808 * Assumes interrupts are blocked. 1809 */ 1810 void 1811 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1812 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1813 { 1814 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1815 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1816 1817 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1818 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1819 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1820 chp->ch_channel, drive, command, blkno, count, features, device), 1821 DEBUG_FUNCS); 1822 1823 KASSERT(drive < wdc->wdc_maxdrives); 1824 1825 if (wdc->select) 1826 wdc->select(chp,drive); 1827 1828 /* Select drive, head, and addressing mode. */ 1829 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1830 (drive << 4) | device); 1831 1832 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1833 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1834 0, features); 1835 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1836 0, count); 1837 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1838 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1839 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1840 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1841 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1842 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1843 } else { 1844 /* previous */ 1845 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1846 0, features >> 8); 1847 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1848 0, count >> 8); 1849 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1850 0, blkno >> 24); 1851 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1852 0, blkno >> 32); 1853 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1854 0, blkno >> 40); 1855 1856 /* current */ 1857 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1858 0, features); 1859 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1860 0, count); 1861 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1862 0, blkno); 1863 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1864 0, blkno >> 8); 1865 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1866 0, blkno >> 16); 1867 } 1868 1869 /* Send command. */ 1870 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1871 return; 1872 } 1873 1874 /* 1875 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1876 * tested by the caller. 1877 */ 1878 void 1879 wdccommandshort(struct ata_channel *chp, int drive, int command) 1880 { 1881 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1882 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1883 1884 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1885 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1886 command), DEBUG_FUNCS); 1887 1888 if (wdc->select) 1889 wdc->select(chp,drive); 1890 1891 /* Select drive. */ 1892 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1893 WDSD_IBM | (drive << 4)); 1894 1895 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1896 } 1897 1898 static void 1899 __wdcerror(struct ata_channel *chp, const char *msg) 1900 { 1901 struct atac_softc *atac = chp->ch_atac; 1902 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1903 1904 if (xfer == NULL) 1905 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1906 chp->ch_channel, msg); 1907 else 1908 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1909 chp->ch_channel, xfer->c_drive, msg); 1910 } 1911 1912 /* 1913 * the bit bucket 1914 */ 1915 void 1916 wdcbit_bucket(struct ata_channel *chp, int size) 1917 { 1918 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1919 1920 for (; size >= 2; size -= 2) 1921 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1922 if (size) 1923 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1924 } 1925 1926 static void 1927 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1928 { 1929 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1930 1931 #ifndef __NO_STRICT_ALIGNMENT 1932 if ((uintptr_t)bf & 1) 1933 goto unaligned; 1934 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1935 goto unaligned; 1936 #endif 1937 1938 if (flags & ATA_DRIVE_NOSTREAM) { 1939 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1940 bus_space_read_multi_4(wdr->data32iot, 1941 wdr->data32ioh, 0, bf, len >> 2); 1942 bf = (char *)bf + (len & ~3); 1943 len &= 3; 1944 } 1945 if (len > 1) { 1946 bus_space_read_multi_2(wdr->cmd_iot, 1947 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1948 bf = (char *)bf + (len & ~1); 1949 len &= 1; 1950 } 1951 } else { 1952 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1953 bus_space_read_multi_stream_4(wdr->data32iot, 1954 wdr->data32ioh, 0, bf, len >> 2); 1955 bf = (char *)bf + (len & ~3); 1956 len &= 3; 1957 } 1958 if (len > 1) { 1959 bus_space_read_multi_stream_2(wdr->cmd_iot, 1960 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1961 bf = (char *)bf + (len & ~1); 1962 len &= 1; 1963 } 1964 } 1965 if (len) 1966 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1967 wdr->cmd_iohs[wd_data], 0); 1968 return; 1969 1970 #ifndef __NO_STRICT_ALIGNMENT 1971 unaligned: 1972 if (flags & ATA_DRIVE_NOSTREAM) { 1973 if (flags & ATA_DRIVE_CAP32) { 1974 while (len > 3) { 1975 uint32_t val; 1976 1977 val = bus_space_read_4(wdr->data32iot, 1978 wdr->data32ioh, 0); 1979 memcpy(bf, &val, 4); 1980 bf = (char *)bf + 4; 1981 len -= 4; 1982 } 1983 } 1984 while (len > 1) { 1985 uint16_t val; 1986 1987 val = bus_space_read_2(wdr->cmd_iot, 1988 wdr->cmd_iohs[wd_data], 0); 1989 memcpy(bf, &val, 2); 1990 bf = (char *)bf + 2; 1991 len -= 2; 1992 } 1993 } else { 1994 if (flags & ATA_DRIVE_CAP32) { 1995 while (len > 3) { 1996 uint32_t val; 1997 1998 val = bus_space_read_stream_4(wdr->data32iot, 1999 wdr->data32ioh, 0); 2000 memcpy(bf, &val, 4); 2001 bf = (char *)bf + 4; 2002 len -= 4; 2003 } 2004 } 2005 while (len > 1) { 2006 uint16_t val; 2007 2008 val = bus_space_read_stream_2(wdr->cmd_iot, 2009 wdr->cmd_iohs[wd_data], 0); 2010 memcpy(bf, &val, 2); 2011 bf = (char *)bf + 2; 2012 len -= 2; 2013 } 2014 } 2015 #endif 2016 } 2017 2018 static void 2019 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2020 { 2021 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2022 2023 #ifndef __NO_STRICT_ALIGNMENT 2024 if ((uintptr_t)bf & 1) 2025 goto unaligned; 2026 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2027 goto unaligned; 2028 #endif 2029 2030 if (flags & ATA_DRIVE_NOSTREAM) { 2031 if (flags & ATA_DRIVE_CAP32) { 2032 bus_space_write_multi_4(wdr->data32iot, 2033 wdr->data32ioh, 0, bf, len >> 2); 2034 bf = (char *)bf + (len & ~3); 2035 len &= 3; 2036 } 2037 if (len) { 2038 bus_space_write_multi_2(wdr->cmd_iot, 2039 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2040 } 2041 } else { 2042 if (flags & ATA_DRIVE_CAP32) { 2043 bus_space_write_multi_stream_4(wdr->data32iot, 2044 wdr->data32ioh, 0, bf, len >> 2); 2045 bf = (char *)bf + (len & ~3); 2046 len &= 3; 2047 } 2048 if (len) { 2049 bus_space_write_multi_stream_2(wdr->cmd_iot, 2050 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2051 } 2052 } 2053 return; 2054 2055 #ifndef __NO_STRICT_ALIGNMENT 2056 unaligned: 2057 if (flags & ATA_DRIVE_NOSTREAM) { 2058 if (flags & ATA_DRIVE_CAP32) { 2059 while (len > 3) { 2060 uint32_t val; 2061 2062 memcpy(&val, bf, 4); 2063 bus_space_write_4(wdr->data32iot, 2064 wdr->data32ioh, 0, val); 2065 bf = (char *)bf + 4; 2066 len -= 4; 2067 } 2068 } 2069 while (len > 1) { 2070 uint16_t val; 2071 2072 memcpy(&val, bf, 2); 2073 bus_space_write_2(wdr->cmd_iot, 2074 wdr->cmd_iohs[wd_data], 0, val); 2075 bf = (char *)bf + 2; 2076 len -= 2; 2077 } 2078 } else { 2079 if (flags & ATA_DRIVE_CAP32) { 2080 while (len > 3) { 2081 uint32_t val; 2082 2083 memcpy(&val, bf, 4); 2084 bus_space_write_stream_4(wdr->data32iot, 2085 wdr->data32ioh, 0, val); 2086 bf = (char *)bf + 4; 2087 len -= 4; 2088 } 2089 } 2090 while (len > 1) { 2091 uint16_t val; 2092 2093 memcpy(&val, bf, 2); 2094 bus_space_write_stream_2(wdr->cmd_iot, 2095 wdr->cmd_iohs[wd_data], 0, val); 2096 bf = (char *)bf + 2; 2097 len -= 2; 2098 } 2099 } 2100 #endif 2101 } 2102
Indexes created Thu Jun 11 00:25:07 UTC 2026