1 /* $NetBSD: wdsc.c,v 1.35 2021/08/07 16:19:00 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)wdsc.c 32 */ 33 34 /*- 35 * Copyright (c) 1996-2004 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Steve C. Woodford. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: wdsc.c,v 1.35 2021/08/07 16:19:00 thorpej Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 71 #include <dev/scsipi/scsi_all.h> 72 #include <dev/scsipi/scsipi_all.h> 73 #include <dev/scsipi/scsiconf.h> 74 75 #include <machine/cpu.h> 76 #include <machine/bus.h> 77 #include <machine/autoconf.h> 78 79 #include <mvme68k/dev/dmavar.h> 80 #include <mvme68k/dev/pccreg.h> 81 #include <mvme68k/dev/pccvar.h> 82 #include <mvme68k/dev/sbicreg.h> 83 #include <mvme68k/dev/sbicvar.h> 84 #include <mvme68k/dev/wdscreg.h> 85 86 #include "ioconf.h" 87 88 void wdsc_pcc_attach(device_t, device_t, void *); 89 int wdsc_pcc_match(device_t, cfdata_t, void *); 90 91 CFATTACH_DECL_NEW(wdsc_pcc, sizeof(struct sbic_softc), 92 wdsc_pcc_match, wdsc_pcc_attach, NULL, NULL); 93 94 void wdsc_enintr(struct sbic_softc *); 95 int wdsc_dmago(struct sbic_softc *, char *, int, int); 96 int wdsc_dmanext(struct sbic_softc *); 97 void wdsc_dmastop(struct sbic_softc *); 98 int wdsc_dmaintr(void *); 99 int wdsc_scsiintr(void *); 100 101 /* 102 * Match for SCSI devices on the onboard WD33C93 chip 103 */ 104 int 105 wdsc_pcc_match(device_t parent, cfdata_t cf, void *aux) 106 { 107 struct pcc_attach_args *pa = aux; 108 109 if (strcmp(pa->pa_name, wdsc_cd.cd_name)) 110 return 0; 111 112 pa->pa_ipl = cf->pcccf_ipl; 113 return 1; 114 } 115 116 /* 117 * Attach the wdsc driver 118 */ 119 void 120 wdsc_pcc_attach(device_t parent, device_t self, void *aux) 121 { 122 struct sbic_softc *sc; 123 struct pcc_attach_args *pa; 124 bus_space_handle_t bush; 125 static struct evcnt evcnt; /* XXXSCW: Temporary hack */ 126 127 sc = device_private(self); 128 sc->sc_dev = self; 129 pa = aux; 130 131 bus_space_map(pa->pa_bust, pa->pa_offset, 0x20, 0, &bush); 132 133 /* 134 * XXXSCW: We *need* an MI, bus_spaced WD33C93 driver... 135 */ 136 sc->sc_sbicp = (sbic_regmap_p) bush; 137 138 sc->sc_driver = (void *) &evcnt; 139 sc->sc_enintr = wdsc_enintr; 140 sc->sc_dmago = wdsc_dmago; 141 sc->sc_dmanext = wdsc_dmanext; 142 sc->sc_dmastop = wdsc_dmastop; 143 sc->sc_dmacmd = 0; 144 145 sc->sc_adapter.adapt_dev = self; 146 sc->sc_adapter.adapt_nchannels = 1; 147 sc->sc_adapter.adapt_openings = 7; 148 sc->sc_adapter.adapt_max_periph = 1; 149 sc->sc_adapter.adapt_ioctl = NULL; 150 sc->sc_adapter.adapt_minphys = sbic_minphys; 151 sc->sc_adapter.adapt_request = sbic_scsi_request; 152 153 sc->sc_channel.chan_adapter = &sc->sc_adapter; 154 sc->sc_channel.chan_bustype = &scsi_bustype; 155 sc->sc_channel.chan_channel = 0; 156 sc->sc_channel.chan_ntargets = 8; 157 sc->sc_channel.chan_nluns = 8; 158 sc->sc_channel.chan_id = 7; 159 160 printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id); 161 162 /* 163 * Everything is a valid DMA address. 164 */ 165 sc->sc_dmamask = 0; 166 167 /* 168 * The onboard WD33C93 of the '147 is usually clocked at 10MHz... 169 * (We use 10 times this for accuracy in later calculations) 170 */ 171 sc->sc_clkfreq = 100; 172 173 /* 174 * Initialise the hardware 175 */ 176 sbicinit(sc); 177 178 /* 179 * Fix up the interrupts 180 */ 181 sc->sc_ipl = pa->pa_ipl & PCC_IMASK; 182 183 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, PCC_ICLEAR); 184 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, PCC_ICLEAR); 185 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 186 187 evcnt_attach_dynamic(&evcnt, EVCNT_TYPE_INTR, pccintr_evcnt(sc->sc_ipl), 188 "disk", device_xname(self)); 189 pccintr_establish(PCCV_DMA, wdsc_dmaintr, sc->sc_ipl, sc, &evcnt); 190 pccintr_establish(PCCV_SCSI, wdsc_scsiintr, sc->sc_ipl, sc, &evcnt); 191 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 192 sc->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 193 194 (void)config_found(self, &sc->sc_channel, scsiprint, CFARGS_NONE); 195 } 196 197 /* 198 * Enable DMA interrupts 199 */ 200 void 201 wdsc_enintr(struct sbic_softc *dev) 202 { 203 204 dev->sc_flags |= SBICF_INTR; 205 206 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 207 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 208 } 209 210 /* 211 * Prime the hardware for a DMA transfer 212 */ 213 int 214 wdsc_dmago(struct sbic_softc *dev, char *addr, int count, int flags) 215 { 216 217 /* 218 * Set up the command word based on flags 219 */ 220 if ((flags & DMAGO_READ) == 0) 221 dev->sc_dmacmd = DMAC_CSR_ENABLE | DMAC_CSR_WRITE; 222 else 223 dev->sc_dmacmd = DMAC_CSR_ENABLE; 224 225 dev->sc_flags |= SBICF_INTR; 226 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 227 228 /* 229 * Prime the hardware. 230 * Note, it's probably not necessary to do this here, since dmanext 231 * is called just prior to the actual transfer. 232 */ 233 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 234 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 235 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 236 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 237 (uint32_t) dev->sc_cur->dc_addr); 238 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 239 (uint32_t) dev->sc_tcnt | (1 << 24)); 240 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 241 242 return dev->sc_tcnt; 243 } 244 245 /* 246 * Prime the hardware for the next DMA transfer 247 */ 248 int 249 wdsc_dmanext(struct sbic_softc *dev) 250 { 251 252 if (dev->sc_cur > dev->sc_last) { 253 /* 254 * Shouldn't happen !! 255 */ 256 printf("wdsc_dmanext at end !!!\n"); 257 wdsc_dmastop(dev); 258 return 0; 259 } 260 261 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 262 263 /* 264 * Load the next DMA address 265 */ 266 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 267 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 268 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 269 pcc_reg_write32(sys_pcc, PCCREG_DMA_DATA_ADDR, 270 (uint32_t) dev->sc_cur->dc_addr); 271 pcc_reg_write32(sys_pcc, PCCREG_DMA_BYTE_COUNT, 272 (uint32_t) dev->sc_tcnt | (1 << 24)); 273 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, dev->sc_dmacmd); 274 275 return dev->sc_tcnt; 276 } 277 278 /* 279 * Stop DMA, and disable interrupts 280 */ 281 void 282 wdsc_dmastop(struct sbic_softc *dev) 283 { 284 int s; 285 286 s = splbio(); 287 288 pcc_reg_write(sys_pcc, PCCREG_DMA_CONTROL, 0); 289 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, dev->sc_ipl | PCC_ICLEAR); 290 291 splx(s); 292 } 293 294 /* 295 * Come here following a DMA interrupt 296 */ 297 int 298 wdsc_dmaintr(void *arg) 299 { 300 struct sbic_softc *dev = arg; 301 int found = 0; 302 303 /* 304 * Really a DMA interrupt? 305 */ 306 if ((pcc_reg_read(sys_pcc, PCCREG_DMA_INTR_CTRL) & 0x80) == 0) 307 return 0; 308 309 /* 310 * Was it a completion interrupt? 311 * XXXSCW Note: Support for other DMA interrupts is required, 312 * eg. buserr 313 */ 314 if (pcc_reg_read(sys_pcc, PCCREG_DMA_CONTROL) & DMAC_CSR_DONE) { 315 ++found; 316 317 pcc_reg_write(sys_pcc, PCCREG_DMA_INTR_CTRL, 318 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 319 } 320 321 return found; 322 } 323 324 /* 325 * Come here for SCSI interrupts 326 */ 327 int 328 wdsc_scsiintr(void *arg) 329 { 330 struct sbic_softc *dev = arg; 331 int found; 332 333 /* 334 * Really a SCSI interrupt? 335 */ 336 if ((pcc_reg_read(sys_pcc, PCCREG_SCSI_INTR_CTRL) & 0x80) == 0) 337 return 0; 338 339 /* 340 * Go handle it 341 */ 342 found = sbicintr(dev); 343 344 /* 345 * Acknowledge and clear the interrupt 346 */ 347 pcc_reg_write(sys_pcc, PCCREG_SCSI_INTR_CTRL, 348 dev->sc_ipl | PCC_IENABLE | PCC_ICLEAR); 349 350 return found; 351 } 352
Indexes created Tue Sep 30 07:10:03 GMT 2025