1 /* $NetBSD: ni_dpm.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __NI_DPM_H__ 26 #define __NI_DPM_H__ 27 28 #include "cypress_dpm.h" 29 #include "btc_dpm.h" 30 #include "nislands_smc.h" 31 32 struct ni_clock_registers { 33 u32 cg_spll_func_cntl; 34 u32 cg_spll_func_cntl_2; 35 u32 cg_spll_func_cntl_3; 36 u32 cg_spll_func_cntl_4; 37 u32 cg_spll_spread_spectrum; 38 u32 cg_spll_spread_spectrum_2; 39 u32 mclk_pwrmgt_cntl; 40 u32 dll_cntl; 41 u32 mpll_ad_func_cntl; 42 u32 mpll_ad_func_cntl_2; 43 u32 mpll_dq_func_cntl; 44 u32 mpll_dq_func_cntl_2; 45 u32 mpll_ss1; 46 u32 mpll_ss2; 47 }; 48 49 struct ni_mc_reg_entry { 50 u32 mclk_max; 51 u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 52 }; 53 54 struct ni_mc_reg_table { 55 u8 last; 56 u8 num_entries; 57 u16 valid_flag; 58 struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 59 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 60 }; 61 62 #define NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 2 63 64 enum ni_dc_cac_level 65 { 66 NISLANDS_DCCAC_LEVEL_0 = 0, 67 NISLANDS_DCCAC_LEVEL_1, 68 NISLANDS_DCCAC_LEVEL_2, 69 NISLANDS_DCCAC_LEVEL_3, 70 NISLANDS_DCCAC_LEVEL_4, 71 NISLANDS_DCCAC_LEVEL_5, 72 NISLANDS_DCCAC_LEVEL_6, 73 NISLANDS_DCCAC_LEVEL_7, 74 NISLANDS_DCCAC_MAX_LEVELS 75 }; 76 77 struct ni_leakage_coeffients 78 { 79 u32 at; 80 u32 bt; 81 u32 av; 82 u32 bv; 83 s32 t_slope; 84 s32 t_intercept; 85 u32 t_ref; 86 }; 87 88 struct ni_cac_data 89 { 90 struct ni_leakage_coeffients leakage_coefficients; 91 u32 i_leakage; 92 s32 leakage_minimum_temperature; 93 u32 pwr_const; 94 u32 dc_cac_value; 95 u32 bif_cac_value; 96 u32 lkge_pwr; 97 u8 mc_wr_weight; 98 u8 mc_rd_weight; 99 u8 allow_ovrflw; 100 u8 num_win_tdp; 101 u8 l2num_win_tdp; 102 u8 lts_truncate_n; 103 }; 104 105 struct ni_cac_weights 106 { 107 u32 weight_tcp_sig0; 108 u32 weight_tcp_sig1; 109 u32 weight_ta_sig; 110 u32 weight_tcc_en0; 111 u32 weight_tcc_en1; 112 u32 weight_tcc_en2; 113 u32 weight_cb_en0; 114 u32 weight_cb_en1; 115 u32 weight_cb_en2; 116 u32 weight_cb_en3; 117 u32 weight_db_sig0; 118 u32 weight_db_sig1; 119 u32 weight_db_sig2; 120 u32 weight_db_sig3; 121 u32 weight_sxm_sig0; 122 u32 weight_sxm_sig1; 123 u32 weight_sxm_sig2; 124 u32 weight_sxs_sig0; 125 u32 weight_sxs_sig1; 126 u32 weight_xbr_0; 127 u32 weight_xbr_1; 128 u32 weight_xbr_2; 129 u32 weight_spi_sig0; 130 u32 weight_spi_sig1; 131 u32 weight_spi_sig2; 132 u32 weight_spi_sig3; 133 u32 weight_spi_sig4; 134 u32 weight_spi_sig5; 135 u32 weight_lds_sig0; 136 u32 weight_lds_sig1; 137 u32 weight_sc; 138 u32 weight_bif; 139 u32 weight_cp; 140 u32 weight_pa_sig0; 141 u32 weight_pa_sig1; 142 u32 weight_vgt_sig0; 143 u32 weight_vgt_sig1; 144 u32 weight_vgt_sig2; 145 u32 weight_dc_sig0; 146 u32 weight_dc_sig1; 147 u32 weight_dc_sig2; 148 u32 weight_dc_sig3; 149 u32 weight_uvd_sig0; 150 u32 weight_uvd_sig1; 151 u32 weight_spare0; 152 u32 weight_spare1; 153 u32 weight_sq_vsp; 154 u32 weight_sq_vsp0; 155 u32 weight_sq_gpr; 156 u32 ovr_mode_spare_0; 157 u32 ovr_val_spare_0; 158 u32 ovr_mode_spare_1; 159 u32 ovr_val_spare_1; 160 u32 vsp; 161 u32 vsp0; 162 u32 gpr; 163 u8 mc_read_weight; 164 u8 mc_write_weight; 165 u32 tid_cnt; 166 u32 tid_unit; 167 u32 l2_lta_window_size; 168 u32 lts_truncate; 169 u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; 170 u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; 171 bool enable_power_containment_by_default; 172 }; 173 174 struct ni_ps { 175 u16 performance_level_count; 176 bool dc_compatible; 177 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 178 }; 179 180 struct ni_power_info { 181 /* must be first! */ 182 struct evergreen_power_info eg; 183 struct ni_clock_registers clock_registers; 184 struct ni_mc_reg_table mc_reg_table; 185 u32 mclk_rtt_mode_threshold; 186 /* flags */ 187 bool use_power_boost_limit; 188 bool support_cac_long_term_average; 189 bool cac_enabled; 190 bool cac_configuration_required; 191 bool driver_calculate_cac_leakage; 192 bool pc_enabled; 193 bool enable_power_containment; 194 bool enable_cac; 195 bool enable_sq_ramping; 196 /* smc offsets */ 197 u16 arb_table_start; 198 u16 fan_table_start; 199 u16 cac_table_start; 200 u16 spll_table_start; 201 /* CAC stuff */ 202 struct ni_cac_data cac_data; 203 u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; 204 const struct ni_cac_weights *cac_weights; 205 u8 lta_window_size; 206 u8 lts_truncate; 207 struct ni_ps current_ps; 208 struct ni_ps requested_ps; 209 /* scratch structs */ 210 SMC_NIslands_MCRegisters smc_mc_reg_table; 211 NISLANDS_SMC_STATETABLE smc_statetable; 212 }; 213 214 #define NISLANDS_INITIAL_STATE_ARB_INDEX 0 215 #define NISLANDS_ACPI_STATE_ARB_INDEX 1 216 #define NISLANDS_ULV_STATE_ARB_INDEX 2 217 #define NISLANDS_DRIVER_STATE_ARB_INDEX 3 218 219 #define NISLANDS_DPM2_MAX_PULSE_SKIP 256 220 221 #define NISLANDS_DPM2_NEAR_TDP_DEC 10 222 #define NISLANDS_DPM2_ABOVE_SAFE_INC 5 223 #define NISLANDS_DPM2_BELOW_SAFE_INC 20 224 225 #define NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 226 227 #define NISLANDS_DPM2_MAXPS_PERCENT_H 90 228 #define NISLANDS_DPM2_MAXPS_PERCENT_M 0 229 230 #define NISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 231 #define NISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 232 #define NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 233 #define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E 234 #define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF 235 236 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, 237 u32 arb_freq_src, u32 arb_freq_dest); 238 void ni_update_current_ps(struct radeon_device *rdev, 239 struct radeon_ps *rps); 240 void ni_update_requested_ps(struct radeon_device *rdev, 241 struct radeon_ps *rps); 242 243 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 244 struct radeon_ps *new_ps, 245 struct radeon_ps *old_ps); 246 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 247 struct radeon_ps *new_ps, 248 struct radeon_ps *old_ps); 249 250 bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 251 252 #endif 253
Indexes created Sat Sep 20 22:09:52 GMT 2025