| /src/tests/dev/sysmon/ |
| t_swwdog.c | 68 struct wdog_mode wm; local in function:testbody
103 strlcpy(wm.wm_name, wc.wc_names, sizeof(wm.wm_name));
104 wm.wm_mode = WDOG_MODE_ETICKLE;
105 wm.wm_period = 1;
106 if (rump_sys_ioctl(fd, WDOGIOC_SMODE, &wm) == -1)
113 wm.wm_mode = WDOG_MODE_DISARMED;
114 rump_sys_ioctl(fd, WDOGIOC_SMODE, &wm);
|
| /src/sbin/wdogctl/ |
| wdogctl.c | 190 struct wdog_mode wm; local in function:enable_kernel
193 prep_wmode(&wm, WDOG_MODE_KTICKLE, name, period);
199 if (ioctl(fd, WDOGIOC_SMODE, &wm) == -1)
208 struct wdog_mode wm; local in function:enable_ext
211 prep_wmode(&wm, WDOG_MODE_ETICKLE, name, period);
216 if (ioctl(fd, WDOGIOC_SMODE, &wm) == -1) {
221 wm.wm_name);
230 struct wdog_mode wm; local in function:enable_user
235 prep_wmode(&wm,
255 if (ioctl(fd, WDOGIOC_SMODE, &wm) == -1)
328 struct wdog_mode wm; local in function:disable
367 struct wdog_mode wm; local in function:list_timers
[all...] |
| /src/sys/dev/sysmon/ |
| sysmon_wdog.c | 205 struct wdog_mode *wm = (void *) data; local in function:sysmonioctl_wdog
207 wm->wm_name[sizeof(wm->wm_name) - 1] = '\0';
208 smw = sysmon_wdog_find(wm->wm_name);
214 wm->wm_mode = smw->smw_mode;
215 wm->wm_period = smw->smw_period;
222 struct wdog_mode *wm = (void *) data; local in function:sysmonioctl_wdog
229 wm->wm_name[sizeof(wm->wm_name) - 1] = '\0';
230 smw = sysmon_wdog_find(wm->wm_name)
251 struct wdog_mode *wm = (void *) data; local in function:sysmonioctl_wdog
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 79 struct dcn_hubbub_wm wm; local in function:dcn10_get_hubbub_state
88 memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
89 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
98 s = &wm.sets[i];
|
| amdgpu_dcn10_hw_sequencer.c | 134 struct dcn_hubbub_wm wm; local in function:dcn10_log_hubbub_state
137 memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
138 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
140 DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
146 s = &wm.sets[i];
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_pm.c | 444 mutex_lock(&dev_priv->wm.wm_mutex);
447 dev_priv->wm.vlv.cxsr = enable;
449 dev_priv->wm.g4x.cxsr = enable;
450 mutex_unlock(&dev_priv->wm.wm_mutex);
478 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
741 * @wm: chip FIFO params
758 const struct intel_watermark_params *wm,
772 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
773 wm->guard_size;
780 if (wm_size > wm->max_wm
876 unsigned int wm; local in function:pnv_update_wm
1130 unsigned int clock, htotal, cpp, width, wm; local in function:g4x_compute_wm
1240 int wm, max_wm; local in function:g4x_raw_plane_wm_compute
1640 unsigned int clock, htotal, cpp, width, wm; local in function:vlv_compute_wm_level
1820 int wm = vlv_compute_wm_level(crtc_state, plane_state, level); local in function:vlv_raw_plane_wm_compute
3199 struct intel_wm_level *wm = &pipe_wm->wm[level]; local in function:ilk_compute_pipe_wm
3292 const struct intel_wm_level *wm = &active->wm[level]; local in function:ilk_merge_wm_level
3333 struct intel_wm_level *wm = &merged->wm[level]; local in function:ilk_wm_merge
3363 struct intel_wm_level *wm = &merged->wm[level]; local in function:ilk_wm_merge
3845 struct skl_plane_wm *wm = local in function:intel_can_enable_sagv
4005 struct skl_wm_level wm = {}; local in function:skl_cursor_allocation
4348 const struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4384 const struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4456 struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4493 struct skl_plane_wm *wm = local in function:skl_allocate_pipe_ddb
4937 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; local in function:skl_build_plane_wm_single
4956 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; local in function:skl_build_plane_wm_uv
5099 const struct skl_plane_wm *wm = local in function:skl_write_plane_wm
5135 const struct skl_plane_wm *wm = local in function:skl_write_cursor_wm
5609 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; local in function:ilk_compute_wm_config
5703 struct skl_plane_wm *wm = &out->planes[plane_id]; local in function:skl_pipe_wm_get_hw_state
5911 struct g4x_wm_values *wm = &dev_priv->wm.g4x; local in function:g4x_wm_get_hw_state
6054 struct vlv_wm_values *wm = &dev_priv->wm.vlv; local in function:vlv_wm_get_hw_state
[all...] |
| i915_drv.h | 828 /* Stores plane specific WM parameters */
1225 * Should be held around atomic WM register writing; also
1226 * protects * intel_crtc->wm.active and
1227 * crtc_state->wm.need_postvbl_update.
1237 } wm; member in struct:drm_i915_private
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_types.h | 607 * It's also used by the watermark code to ignore wm calculations on
608 * this plane. They're calculated by the linked plane's wm code.
664 struct intel_wm_level wm[5]; member in struct:intel_pipe_wm
673 struct skl_wm_level wm[8]; member in struct:skl_plane_wm
692 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; member in struct:vlv_wm_state
710 struct g4x_pipe_wm wm; member in struct:g4x_wm_state
738 /* gen9+ only needs 1-step wm programming */
991 struct intel_crtc_wm_state wm; member in struct:intel_crtc_state
1092 } wm; member in struct:intel_crtc
|
| intel_display.c | 4797 /* ignore any reset values/BIOS leftovers in the WM registers */
12166 * per-plane wm computation to the .check_plane() hook, and
13068 saved_state->wm = crtc_state->wm;
13765 struct skl_pipe_wm wm; member in struct:verify_wm_state::skl_hw_state
13780 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13781 sw_wm = &new_crtc_state->wm.skl.optimal;
13786 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13798 hw_plane_wm = &hw->wm.planes[plane];
13803 if (skl_wm_level_equals(&hw_plane_wm->wm[level]
[all...] |
