1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2024 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Make these flags read-only so that all uses go via 26 aarch64_set_asm_isa_flags. */ 27 #ifndef GENERATOR_FILE 28 #undef aarch64_asm_isa_flags 29 #define aarch64_asm_isa_flags \ 30 ((aarch64_feature_flags) global_options.x_aarch64_asm_isa_flags) 31 #undef aarch64_isa_flags 32 #define aarch64_isa_flags \ 33 ((aarch64_feature_flags) global_options.x_aarch64_isa_flags) 34 #endif 35 36 /* Target CPU builtins. */ 37 #define TARGET_CPU_CPP_BUILTINS() \ 38 aarch64_cpu_cpp_builtins (pfile) 39 40 41 43 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 44 45 /* Target machine storage layout. */ 46 47 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 48 if (GET_MODE_CLASS (MODE) == MODE_INT \ 49 && GET_MODE_SIZE (MODE) < 4) \ 50 { \ 51 if (MODE == QImode || MODE == HImode) \ 52 { \ 53 MODE = SImode; \ 54 } \ 55 } 56 57 /* Bits are always numbered from the LSBit. */ 58 #define BITS_BIG_ENDIAN 0 59 60 /* Big/little-endian flavour. */ 61 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 62 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 63 64 /* AdvSIMD is supported in the default configuration, unless disabled by 65 -mgeneral-regs-only or by the +nosimd extension. The set of available 66 instructions is then subdivided into: 67 68 - the "base" set, available both in SME streaming mode and in 69 non-streaming mode 70 71 - the full set, available only in non-streaming mode. */ 72 #define TARGET_BASE_SIMD (AARCH64_ISA_SIMD) 73 #define TARGET_SIMD (AARCH64_ISA_SIMD && AARCH64_ISA_SM_OFF) 74 #define TARGET_FLOAT (AARCH64_ISA_FP) 75 76 #define UNITS_PER_WORD 8 77 78 #define UNITS_PER_VREG 16 79 80 #define PARM_BOUNDARY 64 81 82 #define STACK_BOUNDARY 128 83 84 #define FUNCTION_BOUNDARY 32 85 86 #define EMPTY_FIELD_BOUNDARY 32 87 88 #define BIGGEST_ALIGNMENT 128 89 90 #define SHORT_TYPE_SIZE 16 91 92 #define INT_TYPE_SIZE 32 93 94 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 95 96 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 97 98 #define LONG_LONG_TYPE_SIZE 64 99 100 #define FLOAT_TYPE_SIZE 32 101 102 #define DOUBLE_TYPE_SIZE 64 103 104 #define LONG_DOUBLE_TYPE_SIZE 128 105 106 /* This value is the amount of bytes a caller is allowed to drop the stack 107 before probing has to be done for stack clash protection. */ 108 #define STACK_CLASH_CALLER_GUARD 1024 109 110 /* This value represents the minimum amount of bytes we expect the function's 111 outgoing arguments to be when stack-clash is enabled. */ 112 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8 113 114 /* This value controls how many pages we manually unroll the loop for when 115 generating stack clash probes. */ 116 #define STACK_CLASH_MAX_UNROLL_PAGES 4 117 118 /* The architecture reserves all bits of the address for hardware use, 119 so the vbit must go into the delta field of pointers to member 120 functions. This is the same config as that in the AArch32 121 port. */ 122 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 123 124 125 /* Emit calls to libgcc helpers for atomic operations for runtime detection 126 of LSE instructions. */ 127 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics) 128 129 /* Align definitions of arrays, unions and structures so that 130 initializations and copies can be made more efficient. This is not 131 ABI-changing, so it only affects places where we can see the 132 definition. Increasing the alignment tends to introduce padding, 133 so don't do this when optimizing for size/conserving stack space. */ 134 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 135 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 136 && (TREE_CODE (EXP) == ARRAY_TYPE \ 137 || TREE_CODE (EXP) == UNION_TYPE \ 138 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 139 140 /* Align global data. */ 141 #define DATA_ALIGNMENT(EXP, ALIGN) \ 142 AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN) 143 144 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 145 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 146 AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN) 147 148 #define STRUCTURE_SIZE_BOUNDARY 8 149 150 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY). */ 151 #define MALLOC_ABI_ALIGNMENT 128 152 153 /* Defined by the ABI */ 154 #define WCHAR_TYPE "unsigned int" 155 #define WCHAR_TYPE_SIZE 32 156 157 /* Using long long breaks -ansi and -std=c90, so these will need to be 158 made conditional for an LLP64 ABI. */ 159 160 #define SIZE_TYPE "long unsigned int" 161 162 #define PTRDIFF_TYPE "long int" 163 164 #define PCC_BITFIELD_TYPE_MATTERS 1 165 166 #ifndef USED_FOR_TARGET 167 168 /* Define an enum of all features (ISA modes, architectures and extensions). 169 The ISA modes must come first. */ 170 enum class aarch64_feature : unsigned char { 171 #define DEF_AARCH64_ISA_MODE(IDENT) IDENT, 172 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) IDENT, 173 #define AARCH64_ARCH(A, B, IDENT, D, E) IDENT, 174 #include "aarch64-isa-modes.def" 175 #include "aarch64-option-extensions.def" 176 #include "aarch64-arches.def" 177 }; 178 179 /* Define unique flags for each of the above. */ 180 #define HANDLE(IDENT) \ 181 constexpr auto AARCH64_FL_##IDENT \ 182 = aarch64_feature_flags (1) << int (aarch64_feature::IDENT); 183 #define DEF_AARCH64_ISA_MODE(IDENT) HANDLE (IDENT) 184 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) HANDLE (IDENT) 185 #define AARCH64_ARCH(A, B, IDENT, D, E) HANDLE (IDENT) 186 #include "aarch64-isa-modes.def" 187 #include "aarch64-option-extensions.def" 188 #include "aarch64-arches.def" 189 #undef HANDLE 190 191 constexpr auto AARCH64_FL_SM_STATE = AARCH64_FL_SM_ON | AARCH64_FL_SM_OFF; 192 193 constexpr unsigned int AARCH64_NUM_ISA_MODES = (0 194 #define DEF_AARCH64_ISA_MODE(IDENT) + 1 195 #include "aarch64-isa-modes.def" 196 ); 197 198 /* The mask of all ISA modes. */ 199 constexpr auto AARCH64_FL_ISA_MODES 200 = (aarch64_feature_flags (1) << AARCH64_NUM_ISA_MODES) - 1; 201 202 /* The default ISA mode, for functions with no attributes that specify 203 something to the contrary. */ 204 constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; 205 206 #endif 207 208 /* Macros to test ISA flags. 209 210 There is intentionally no macro for AARCH64_FL_CRYPTO, since this flag bit 211 is not always set when its constituent features are present. 212 Check (TARGET_AES && TARGET_SHA2) instead. */ 213 214 #define AARCH64_ISA_SM_OFF (aarch64_isa_flags & AARCH64_FL_SM_OFF) 215 #define AARCH64_ISA_SM_ON (aarch64_isa_flags & AARCH64_FL_SM_ON) 216 #define AARCH64_ISA_ZA_ON (aarch64_isa_flags & AARCH64_FL_ZA_ON) 217 #define AARCH64_ISA_MODE (aarch64_isa_flags & AARCH64_FL_ISA_MODES) 218 #define AARCH64_ISA_V8A (aarch64_isa_flags & AARCH64_FL_V8A) 219 #define AARCH64_ISA_V8_1A (aarch64_isa_flags & AARCH64_FL_V8_1A) 220 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 221 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 222 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 223 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 224 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) 225 #define AARCH64_ISA_V8_2A (aarch64_isa_flags & AARCH64_FL_V8_2A) 226 #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) 227 #define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) 228 #define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) 229 #define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES) 230 #define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) 231 #define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) 232 #define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) 233 #define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME) 234 #define AARCH64_ISA_SME_I16I64 (aarch64_isa_flags & AARCH64_FL_SME_I16I64) 235 #define AARCH64_ISA_SME_F64F64 (aarch64_isa_flags & AARCH64_FL_SME_F64F64) 236 #define AARCH64_ISA_SME2 (aarch64_isa_flags & AARCH64_FL_SME2) 237 #define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A) 238 #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) 239 #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) 240 #define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) 241 #define AARCH64_ISA_V8_4A (aarch64_isa_flags & AARCH64_FL_V8_4A) 242 #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) 243 #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) 244 #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) 245 #define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC) 246 #define AARCH64_ISA_RCPC8_4 ((AARCH64_ISA_RCPC && AARCH64_ISA_V8_4A) \ 247 || (aarch64_isa_flags & AARCH64_FL_RCPC3)) 248 #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) 249 #define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A) 250 #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) 251 #define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG) 252 #define AARCH64_ISA_V8_6A (aarch64_isa_flags & AARCH64_FL_V8_6A) 253 #define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM) 254 #define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM) 255 #define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) 256 #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) 257 #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) 258 #define AARCH64_ISA_RCPC3 (aarch64_isa_flags & AARCH64_FL_RCPC3) 259 #define AARCH64_ISA_V8R (aarch64_isa_flags & AARCH64_FL_V8R) 260 #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) 261 #define AARCH64_ISA_V8_7A (aarch64_isa_flags & AARCH64_FL_V8_7A) 262 #define AARCH64_ISA_V8_8A (aarch64_isa_flags & AARCH64_FL_V8_8A) 263 #define AARCH64_ISA_V8_9A (aarch64_isa_flags & AARCH64_FL_V8_9A) 264 #define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A) 265 #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A) 266 #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A) 267 #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) 268 #define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A) 269 #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) 270 #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) 271 #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) 272 #define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128) 273 #define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE) 274 #define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS) 275 276 /* The current function is a normal non-streaming function. */ 277 #define TARGET_NON_STREAMING (AARCH64_ISA_SM_OFF) 278 279 /* The current function has a streaming body. */ 280 #define TARGET_STREAMING (AARCH64_ISA_SM_ON) 281 282 /* The current function has a streaming-compatible body. */ 283 #define TARGET_STREAMING_COMPATIBLE \ 284 ((aarch64_isa_flags & AARCH64_FL_SM_STATE) == 0) 285 286 /* PSTATE.ZA is enabled in the current function body. */ 287 #define TARGET_ZA (AARCH64_ISA_ZA_ON) 288 /* AARCH64_FL options necessary for system register implementation. */ 289 290 /* Define AARCH64_FL aliases for architectural features which are protected 291 by -march flags in binutils but which receive no special treatment by GCC. 292 293 Such flags are inherited from the Binutils definition of system registers 294 and are mapped to the architecture in which the feature is implemented. */ 295 #define AARCH64_FL_RAS AARCH64_FL_V8A 296 #define AARCH64_FL_LOR AARCH64_FL_V8_1A 297 #define AARCH64_FL_PAN AARCH64_FL_V8_1A 298 #define AARCH64_FL_AMU AARCH64_FL_V8_4A 299 #define AARCH64_FL_SCXTNUM AARCH64_FL_V8_5A 300 #define AARCH64_FL_ID_PFR2 AARCH64_FL_V8_5A 301 302 /* Armv8.9-A extension feature bits defined in Binutils but absent from GCC, 303 aliased to their base architecture. */ 304 #define AARCH64_FL_AIE AARCH64_FL_V8_9A 305 #define AARCH64_FL_DEBUGv8p9 AARCH64_FL_V8_9A 306 #define AARCH64_FL_FGT2 AARCH64_FL_V8_9A 307 #define AARCH64_FL_ITE AARCH64_FL_V8_9A 308 #define AARCH64_FL_PFAR AARCH64_FL_V8_9A 309 #define AARCH64_FL_PMUv3_ICNTR AARCH64_FL_V8_9A 310 #define AARCH64_FL_PMUv3_SS AARCH64_FL_V8_9A 311 #define AARCH64_FL_PMUv3p9 AARCH64_FL_V8_9A 312 #define AARCH64_FL_RASv2 AARCH64_FL_V8_9A 313 #define AARCH64_FL_S1PIE AARCH64_FL_V8_9A 314 #define AARCH64_FL_S1POE AARCH64_FL_V8_9A 315 #define AARCH64_FL_S2PIE AARCH64_FL_V8_9A 316 #define AARCH64_FL_S2POE AARCH64_FL_V8_9A 317 #define AARCH64_FL_SCTLR2 AARCH64_FL_V8_9A 318 #define AARCH64_FL_SEBEP AARCH64_FL_V8_9A 319 #define AARCH64_FL_SPE_FDS AARCH64_FL_V8_9A 320 #define AARCH64_FL_TCR2 AARCH64_FL_V8_9A 321 322 /* SHA2 is an optional extension to AdvSIMD. */ 323 #define TARGET_SHA2 (AARCH64_ISA_SHA2) 324 325 /* SHA3 is an optional extension to AdvSIMD. */ 326 #define TARGET_SHA3 (AARCH64_ISA_SHA3) 327 328 /* AES is an optional extension to AdvSIMD. */ 329 #define TARGET_AES (AARCH64_ISA_AES) 330 331 /* SM is an optional extension to AdvSIMD. */ 332 #define TARGET_SM4 (AARCH64_ISA_SM4) 333 334 /* FP16FML is an optional extension to AdvSIMD. */ 335 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) 336 337 /* CRC instructions that can be enabled through +crc arch extension. */ 338 #define TARGET_CRC32 (AARCH64_ISA_CRC) 339 340 /* Atomic instructions that can be enabled through the +lse extension. */ 341 #define TARGET_LSE (AARCH64_ISA_LSE) 342 343 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ 344 #define TARGET_FP_F16INST (AARCH64_ISA_F16) 345 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) 346 347 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ 348 #define TARGET_DOTPROD (AARCH64_ISA_DOTPROD) 349 350 /* SVE instructions, enabled through +sve. */ 351 #define TARGET_SVE (AARCH64_ISA_SVE) 352 353 /* SVE2 instructions, enabled through +sve2. */ 354 #define TARGET_SVE2 (AARCH64_ISA_SVE2) 355 356 /* SVE2 AES instructions, enabled through +sve2-aes. */ 357 #define TARGET_SVE2_AES (AARCH64_ISA_SVE2_AES && TARGET_NON_STREAMING) 358 359 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ 360 #define TARGET_SVE2_BITPERM (AARCH64_ISA_SVE2_BITPERM && TARGET_NON_STREAMING) 361 362 /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ 363 #define TARGET_SVE2_SHA3 (AARCH64_ISA_SVE2_SHA3 && TARGET_NON_STREAMING) 364 365 /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ 366 #define TARGET_SVE2_SM4 (AARCH64_ISA_SVE2_SM4 && TARGET_NON_STREAMING) 367 368 /* SME instructions, enabled through +sme. Note that this does not 369 imply anything about the state of PSTATE.SM. */ 370 #define TARGET_SME (AARCH64_ISA_SME) 371 372 /* Same with streaming mode enabled. */ 373 #define TARGET_STREAMING_SME (TARGET_STREAMING && TARGET_SME) 374 375 /* The FEAT_SME_I16I64 extension to SME, enabled through +sme-i16i64. */ 376 #define TARGET_SME_I16I64 (AARCH64_ISA_SME_I16I64) 377 378 /* The FEAT_SME_F64F64 extension to SME, enabled through +sme-f64f64. */ 379 #define TARGET_SME_F64F64 (AARCH64_ISA_SME_F64F64) 380 381 /* SME2 instructions, enabled through +sme2. */ 382 #define TARGET_SME2 (AARCH64_ISA_SME2) 383 384 /* Same with streaming mode enabled. */ 385 #define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2) 386 387 /* ARMv8.3-A features. */ 388 #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A) 389 390 /* Javascript conversion instruction from Armv8.3-a. */ 391 #define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3A) 392 393 /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ 394 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) 395 396 /* Floating-point rounding instructions from Armv8.5-a. */ 397 #define TARGET_FRINT (AARCH64_ISA_V8_5A && TARGET_FLOAT) 398 399 /* TME instructions are enabled. */ 400 #define TARGET_TME (AARCH64_ISA_TME) 401 402 /* Random number instructions from Armv8.5-a. */ 403 #define TARGET_RNG (AARCH64_ISA_RNG) 404 405 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */ 406 #define TARGET_MEMTAG (AARCH64_ISA_MEMTAG) 407 408 /* I8MM instructions are enabled through +i8mm. */ 409 #define TARGET_I8MM (AARCH64_ISA_I8MM) 410 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM) 411 412 /* F32MM instructions are enabled through +f32mm. */ 413 #define TARGET_SVE_F32MM (AARCH64_ISA_F32MM) 414 415 /* F64MM instructions are enabled through +f64mm. */ 416 #define TARGET_SVE_F64MM (AARCH64_ISA_F64MM) 417 418 /* BF16 instructions are enabled through +bf16. */ 419 #define TARGET_BF16_FP (AARCH64_ISA_BF16) 420 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) 421 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) 422 423 /* PAUTH instructions are enabled through +pauth. */ 424 #define TARGET_PAUTH (AARCH64_ISA_PAUTH) 425 426 /* BTI instructions exist from Armv8.5-a onwards. Their automatic use is 427 enabled through -mbranch-protection by using NOP-space instructions, 428 but this TARGET_ is used for defining BTI-related ACLE things. */ 429 #define TARGET_BTI (AARCH64_ISA_V8_5A) 430 431 /* MOPS instructions are enabled through +mops. */ 432 #define TARGET_MOPS (AARCH64_ISA_MOPS) 433 434 /* LS64 instructions are enabled through +ls64. */ 435 #define TARGET_LS64 (AARCH64_ISA_LS64) 436 437 /* CSSC instructions are enabled through +cssc. */ 438 #define TARGET_CSSC (AARCH64_ISA_CSSC) 439 440 /* Make sure this is always defined so we don't have to check for ifdefs 441 but rather use normal ifs. */ 442 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 443 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 444 #else 445 #undef TARGET_FIX_ERR_A53_835769_DEFAULT 446 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 447 #endif 448 449 /* SB instruction is enabled through +sb. */ 450 #define TARGET_SB (AARCH64_ISA_SB) 451 452 /* RCPC loads from Armv8.3-a. */ 453 #define TARGET_RCPC (AARCH64_ISA_RCPC) 454 455 /* The RCPC2 extensions from Armv8.4-a that allow immediate offsets to LDAPR 456 and sign-extending versions.*/ 457 #define TARGET_RCPC2 (AARCH64_ISA_RCPC8_4) 458 459 /* RCPC3 (Release Consistency) extensions, optional from Armv8.2-a. */ 460 #define TARGET_RCPC3 (AARCH64_ISA_RCPC3) 461 462 /* Apply the workaround for Cortex-A53 erratum 835769. */ 463 #define TARGET_FIX_ERR_A53_835769 \ 464 ((aarch64_fix_a53_err835769 == 2) \ 465 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 466 467 /* Make sure this is always defined so we don't have to check for ifdefs 468 but rather use normal ifs. */ 469 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 470 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 471 #else 472 #undef TARGET_FIX_ERR_A53_843419_DEFAULT 473 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 474 #endif 475 476 /* Apply the workaround for Cortex-A53 erratum 843419. */ 477 #define TARGET_FIX_ERR_A53_843419 \ 478 ((aarch64_fix_a53_err843419 == 2) \ 479 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 480 481 /* ARMv8.1-A Adv.SIMD support. */ 482 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 483 484 /* Armv9.4-A features. */ 485 #define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A) 486 487 /* 128-bit System Registers and Instructions from Armv9.4-a are enabled 488 through +d128. */ 489 #define TARGET_D128 (AARCH64_ISA_D128) 490 491 /* Armv8.9-A/9.4-A Translation Hardening Extension system registers are 492 enabled through +the. */ 493 #define TARGET_THE (AARCH64_ISA_THE) 494 495 /* Armv9.4-A Guarded Control Stack extension system registers are 496 enabled through +gcs. */ 497 #define TARGET_GCS (AARCH64_ISA_GCS) 498 499 500 /* Standard register usage. */ 501 502 /* 31 64-bit general purpose registers R0-R30: 503 R30 LR (link register) 504 R29 FP (frame pointer) 505 R19-R28 Callee-saved registers 506 R18 The platform register; use as temporary register. 507 R17 IP1 The second intra-procedure-call temporary register 508 (can be used by call veneers and PLT code); otherwise use 509 as a temporary register 510 R16 IP0 The first intra-procedure-call temporary register (can 511 be used by call veneers and PLT code); otherwise use as a 512 temporary register 513 R9-R15 Temporary registers 514 R8 Structure value parameter / temporary register 515 R0-R7 Parameter/result registers 516 517 SP stack pointer, encoded as X/R31 where permitted. 518 ZR zero register, encoded as X/R31 elsewhere 519 520 32 x 128-bit floating-point/vector registers 521 V16-V31 Caller-saved (temporary) registers 522 V8-V15 Callee-saved registers 523 V0-V7 Parameter/result registers 524 525 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 526 significant bits. Unlike AArch32 S1 is not packed into D0, etc. 527 528 P0-P7 Predicate low registers: valid in all predicate contexts 529 P8-P15 Predicate high registers: used as scratch space 530 531 FFR First Fault Register, a fixed-use SVE predicate register 532 FFRT FFR token: a fake register used for modelling dependencies 533 534 VG Pseudo "vector granules" register 535 536 VG is the number of 64-bit elements in an SVE vector. We define 537 it as a hard register so that we can easily map it to the DWARF VG 538 register. GCC internally uses the poly_int variable aarch64_sve_vg 539 instead. */ 540 541 #define FIXED_REGISTERS \ 542 { \ 543 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 544 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 545 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 546 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 547 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 548 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 549 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 550 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 551 1, 1, 1, 1, /* SFP, AP, CC, VG */ \ 552 0, 0, 0, 0, 0, 0, 0, 0, /* P0 - P7 */ \ 553 0, 0, 0, 0, 0, 0, 0, 0, /* P8 - P15 */ \ 554 1, 1, /* FFR and FFRT */ \ 555 1, 1, 1, 1, 1, 1, 1, 1 /* Fake registers */ \ 556 } 557 558 /* X30 is marked as caller-saved which is in line with regular function call 559 behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does 560 that for regular function calls and avoids it for sibcalls. X30 is 561 considered live for sibcalls; EPILOGUE_USES helps achieve that by returning 562 true but not until function epilogues have been generated. This ensures 563 that X30 is available for use in leaf functions if needed. */ 564 565 #define CALL_REALLY_USED_REGISTERS \ 566 { \ 567 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 568 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 569 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 570 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 571 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 572 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 573 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 574 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 575 1, 1, 1, 0, /* SFP, AP, CC, VG */ \ 576 1, 1, 1, 1, 1, 1, 1, 1, /* P0 - P7 */ \ 577 1, 1, 1, 1, 1, 1, 1, 1, /* P8 - P15 */ \ 578 1, 1, /* FFR and FFRT */ \ 579 0, 0, 0, 0, 0, 0, 0, 0 /* Fake registers */ \ 580 } 581 582 #define REGISTER_NAMES \ 583 { \ 584 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 585 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 586 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 587 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 588 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 589 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 590 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 591 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 592 "sfp", "ap", "cc", "vg", \ 593 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", \ 594 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", \ 595 "ffr", "ffrt", \ 596 "lowering", "tpidr2_block", "sme_state", "tpidr2_setup", \ 597 "za_free", "za_saved", "za", "zt0" \ 598 } 599 600 /* Generate the register aliases for core register N */ 601 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 602 {"w" # N, R0_REGNUM + (N)} 603 604 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 605 {"d" # N, V0_REGNUM + (N)}, \ 606 {"s" # N, V0_REGNUM + (N)}, \ 607 {"h" # N, V0_REGNUM + (N)}, \ 608 {"b" # N, V0_REGNUM + (N)}, \ 609 {"z" # N, V0_REGNUM + (N)} 610 611 #define P_ALIASES(N) {"pn" # N, P0_REGNUM + (N)} 612 613 /* Provide aliases for all of the ISA defined register name forms. 614 These aliases are convenient for use in the clobber lists of inline 615 asm statements. */ 616 617 #define ADDITIONAL_REGISTER_NAMES \ 618 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 619 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 620 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 621 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 622 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 623 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 624 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 625 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 626 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 627 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 628 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 629 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 630 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 631 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 632 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 633 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31), \ 634 P_ALIASES(0), P_ALIASES(1), P_ALIASES(2), P_ALIASES(3), \ 635 P_ALIASES(4), P_ALIASES(5), P_ALIASES(6), P_ALIASES(7), \ 636 P_ALIASES(8), P_ALIASES(9), P_ALIASES(10), P_ALIASES(11), \ 637 P_ALIASES(12), P_ALIASES(13), P_ALIASES(14), P_ALIASES(15) \ 638 } 639 640 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO)) 641 642 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 643 the stack pointer does not matter. This is only true if the function 644 uses alloca. */ 645 #define EXIT_IGNORE_STACK (cfun->calls_alloca) 646 647 #define STATIC_CHAIN_REGNUM R18_REGNUM 648 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 649 #define FRAME_POINTER_REGNUM SFP_REGNUM 650 #define STACK_POINTER_REGNUM SP_REGNUM 651 #define ARG_POINTER_REGNUM AP_REGNUM 652 #define FIRST_PSEUDO_REGISTER (LAST_FAKE_REGNUM + 1) 653 654 /* The number of argument registers available for each class. */ 655 #define NUM_ARG_REGS 8 656 #define NUM_FP_ARG_REGS 8 657 #define NUM_PR_ARG_REGS 4 658 659 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 660 four members. */ 661 #define HA_MAX_NUM_FLDS 4 662 663 /* External dwarf register number scheme. These number are used to 664 identify registers in dwarf debug information, the values are 665 defined by the AArch64 ABI. The numbering scheme is independent of 666 GCC's internal register numbering scheme. */ 667 668 #define AARCH64_DWARF_R0 0 669 670 /* The number of R registers, note 31! not 32. */ 671 #define AARCH64_DWARF_NUMBER_R 31 672 673 #define AARCH64_DWARF_SP 31 674 #define AARCH64_DWARF_VG 46 675 #define AARCH64_DWARF_P0 48 676 #define AARCH64_DWARF_V0 64 677 678 /* The number of V registers. */ 679 #define AARCH64_DWARF_NUMBER_V 32 680 681 /* For signal frames we need to use an alternative return column. This 682 value must not correspond to a hard register and must be out of the 683 range of DWARF_FRAME_REGNUM(). */ 684 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 685 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 686 687 /* We add 1 extra frame register for use as the 688 DWARF_ALT_FRAME_RETURN_COLUMN. */ 689 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 690 691 692 #define DEBUGGER_REGNO(REGNO) aarch64_debugger_regno (REGNO) 693 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 694 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 695 as the default definition in dwarf2out.cc. */ 696 #undef DWARF_FRAME_REGNUM 697 #define DWARF_FRAME_REGNUM(REGNO) DEBUGGER_REGNO (REGNO) 698 699 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 700 701 #define DWARF2_UNWIND_INFO 1 702 703 /* Use R0 through R3 to pass exception handling information. */ 704 #define EH_RETURN_DATA_REGNO(N) \ 705 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 706 707 /* Select a format to encode pointers in exception handling data. */ 708 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 709 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 710 711 /* Output the assembly strings we want to add to a function definition. */ 712 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 713 aarch64_declare_function_name (STR, NAME, DECL) 714 715 /* Output assembly strings for alias definition. */ 716 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \ 717 aarch64_asm_output_alias (STR, DECL, TARGET) 718 719 /* Output assembly strings for undefined extern symbols. */ 720 #undef ASM_OUTPUT_EXTERNAL 721 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \ 722 aarch64_asm_output_external (STR, DECL, NAME) 723 724 /* Output assembly strings after .cfi_startproc is emitted. */ 725 #define ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc 726 727 /* For EH returns X4 is a flag that is set in the EH return 728 code paths and then X5 and X6 contain the stack adjustment 729 and return address respectively. */ 730 #define EH_RETURN_TAKEN_RTX gen_rtx_REG (Pmode, R4_REGNUM) 731 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R5_REGNUM) 732 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, R6_REGNUM) 733 734 #undef TARGET_COMPUTE_FRAME_LAYOUT 735 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame 736 737 /* Register in which the structure value is to be returned. */ 738 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 739 740 /* Non-zero if REGNO is part of the Core register set. 741 742 The rather unusual way of expressing this check is to avoid 743 warnings when building the compiler when R0_REGNUM is 0 and REGNO 744 is unsigned. */ 745 #define GP_REGNUM_P(REGNO) \ 746 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 747 748 /* Registers known to be preserved over a BL instruction. This consists of the 749 GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the 750 BL instruction itself, while the x16 and x17 registers may be used by 751 veneers which can be inserted by the linker. */ 752 #define STUB_REGNUM_P(REGNO) \ 753 (GP_REGNUM_P (REGNO) \ 754 && (REGNO) != R16_REGNUM \ 755 && (REGNO) != R17_REGNUM \ 756 && (REGNO) != R30_REGNUM) \ 757 758 #define W8_W11_REGNUM_P(REGNO) \ 759 IN_RANGE (REGNO, R8_REGNUM, R11_REGNUM) 760 761 #define W12_W15_REGNUM_P(REGNO) \ 762 IN_RANGE (REGNO, R12_REGNUM, R15_REGNUM) 763 764 #define FP_REGNUM_P(REGNO) \ 765 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 766 767 #define FP_LO_REGNUM_P(REGNO) \ 768 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 769 770 #define FP_LO8_REGNUM_P(REGNO) \ 771 (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) 772 773 #define PR_REGNUM_P(REGNO)\ 774 (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) 775 776 #define PR_LO_REGNUM_P(REGNO)\ 777 (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM)) 778 779 #define FP_SIMD_SAVED_REGNUM_P(REGNO) \ 780 (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM)) 781 782 #define FAKE_REGNUM_P(REGNO) \ 783 IN_RANGE (REGNO, FIRST_FAKE_REGNUM, LAST_FAKE_REGNUM) 784 785 /* Register and constant classes. */ 787 788 enum reg_class 789 { 790 NO_REGS, 791 W8_W11_REGS, 792 W12_W15_REGS, 793 TAILCALL_ADDR_REGS, 794 STUB_REGS, 795 GENERAL_REGS, 796 STACK_REG, 797 POINTER_REGS, 798 FP_LO8_REGS, 799 FP_LO_REGS, 800 FP_REGS, 801 POINTER_AND_FP_REGS, 802 PR_LO_REGS, 803 PR_HI_REGS, 804 PR_REGS, 805 FFR_REGS, 806 PR_AND_FFR_REGS, 807 FAKE_REGS, 808 ALL_REGS, 809 LIM_REG_CLASSES /* Last */ 810 }; 811 812 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 813 814 #define REG_CLASS_NAMES \ 815 { \ 816 "NO_REGS", \ 817 "W8_W11_REGS", \ 818 "W12_W15_REGS", \ 819 "TAILCALL_ADDR_REGS", \ 820 "STUB_REGS", \ 821 "GENERAL_REGS", \ 822 "STACK_REG", \ 823 "POINTER_REGS", \ 824 "FP_LO8_REGS", \ 825 "FP_LO_REGS", \ 826 "FP_REGS", \ 827 "POINTER_AND_FP_REGS", \ 828 "PR_LO_REGS", \ 829 "PR_HI_REGS", \ 830 "PR_REGS", \ 831 "FFR_REGS", \ 832 "PR_AND_FFR_REGS", \ 833 "FAKE_REGS", \ 834 "ALL_REGS" \ 835 } 836 837 #define REG_CLASS_CONTENTS \ 838 { \ 839 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 840 { 0x00000f00, 0x00000000, 0x00000000 }, /* W8_W11_REGS */ \ 841 { 0x0000f000, 0x00000000, 0x00000000 }, /* W12_W15_REGS */ \ 842 { 0x00030000, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 843 { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \ 844 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 845 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 846 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 847 { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ 848 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 849 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 850 { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ 851 { 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \ 852 { 0x00000000, 0x00000000, 0x000ff000 }, /* PR_HI_REGS */ \ 853 { 0x00000000, 0x00000000, 0x000ffff0 }, /* PR_REGS */ \ 854 { 0x00000000, 0x00000000, 0x00300000 }, /* FFR_REGS */ \ 855 { 0x00000000, 0x00000000, 0x003ffff0 }, /* PR_AND_FFR_REGS */ \ 856 { 0x00000000, 0x00000000, 0x3fc00000 }, /* FAKE_REGS */ \ 857 { 0xffffffff, 0xffffffff, 0x000fffff } /* ALL_REGS */ \ 858 } 859 860 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 861 862 #define INDEX_REG_CLASS GENERAL_REGS 863 #define BASE_REG_CLASS POINTER_REGS 864 865 /* Register pairs used to eliminate unneeded registers that point into 866 the stack frame. */ 867 #define ELIMINABLE_REGS \ 868 { \ 869 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 870 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 871 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 872 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 873 } 874 875 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 876 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 877 878 /* CPU/ARCH option handling. */ 879 #include "config/aarch64/aarch64-opts.h" 880 881 enum target_cpus 882 { 883 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \ 884 TARGET_CPU_##INTERNAL_IDENT, 885 #include "aarch64-cores.def" 886 }; 887 888 /* If there is no CPU defined at configure, use generic as default. */ 889 #ifndef TARGET_CPU_DEFAULT 890 # define TARGET_CPU_DEFAULT TARGET_CPU_generic_armv8_a 891 #endif 892 893 /* If inserting NOP before a mult-accumulate insn remember to adjust the 894 length so that conditional branching code is updated appropriately. */ 895 #define ADJUST_INSN_LENGTH(insn, length) \ 896 do \ 897 { \ 898 if (aarch64_madd_needs_nop (insn)) \ 899 length += 4; \ 900 } while (0) 901 902 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 903 aarch64_final_prescan_insn (INSN); \ 904 905 /* The processor for which instructions should be scheduled. */ 906 extern enum aarch64_processor aarch64_tune; 907 908 /* RTL generation support. */ 909 #define INIT_EXPANDERS aarch64_init_expanders () 910 911 913 /* Stack layout; function entry, exit and calling. */ 914 #define STACK_GROWS_DOWNWARD 1 915 916 #define FRAME_GROWS_DOWNWARD 1 917 918 #define ACCUMULATE_OUTGOING_ARGS 1 919 920 #define FIRST_PARM_OFFSET(FNDECL) 0 921 922 /* Fix for VFP */ 923 #define LIBCALL_VALUE(MODE) \ 924 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 925 926 #define DEFAULT_PCC_STRUCT_RETURN 0 927 928 #if defined(HAVE_POLY_INT_H) && defined(GCC_VEC_H) 929 struct GTY (()) aarch64_frame 930 { 931 /* The offset from the bottom of the static frame (the bottom of the 932 outgoing arguments) of each register save slot, or -2 if no save is 933 needed. */ 934 poly_int64 reg_offset[LAST_SAVED_REGNUM + 1]; 935 936 /* The list of GPRs, FPRs and predicate registers that have nonnegative 937 entries in reg_offset. The registers are listed in order of 938 increasing offset (rather than increasing register number). */ 939 vec<unsigned, va_gc_atomic> *saved_gprs; 940 vec<unsigned, va_gc_atomic> *saved_fprs; 941 vec<unsigned, va_gc_atomic> *saved_prs; 942 943 /* The offset from the base of the frame of a 64-bit slot whose low 944 bit contains the incoming value of PSTATE.SM. This slot must be 945 within reach of the hard frame pointer. 946 947 The offset is -1 if such a slot isn't needed. */ 948 poly_int64 old_svcr_offset; 949 950 /* The number of extra stack bytes taken up by register varargs. 951 This area is allocated by the callee at the very top of the 952 frame. This value is rounded up to a multiple of 953 STACK_BOUNDARY. */ 954 HOST_WIDE_INT saved_varargs_size; 955 956 /* The number of bytes between the bottom of the static frame (the bottom 957 of the outgoing arguments) and the bottom of the register save area. 958 This value is always a multiple of STACK_BOUNDARY. */ 959 poly_int64 bytes_below_saved_regs; 960 961 /* The number of bytes between the bottom of the static frame (the bottom 962 of the outgoing arguments) and the hard frame pointer. This value is 963 always a multiple of STACK_BOUNDARY. */ 964 poly_int64 bytes_below_hard_fp; 965 966 /* The number of bytes between the top of the locals area and the top 967 of the frame (the incomming SP). This value is always a multiple of 968 STACK_BOUNDARY. */ 969 poly_int64 bytes_above_locals; 970 971 /* The number of bytes between the hard_frame_pointer and the top of 972 the frame (the incomming SP). This value is always a multiple of 973 STACK_BOUNDARY. */ 974 poly_int64 bytes_above_hard_fp; 975 976 /* The size of the frame, i.e. the number of bytes between the bottom 977 of the outgoing arguments and the incoming SP. This value is always 978 a multiple of STACK_BOUNDARY. */ 979 poly_int64 frame_size; 980 981 /* The size of the initial stack adjustment before saving callee-saves. */ 982 poly_int64 initial_adjust; 983 984 /* The writeback value when pushing callee-save registers. 985 It is zero when no push is used. */ 986 HOST_WIDE_INT callee_adjust; 987 988 /* The size of the stack adjustment before saving or after restoring 989 SVE registers. */ 990 poly_int64 sve_callee_adjust; 991 992 /* The size of the stack adjustment after saving callee-saves. */ 993 poly_int64 final_adjust; 994 995 /* Store FP,LR and setup a frame pointer. */ 996 bool emit_frame_chain; 997 998 /* In each frame, we can associate up to two register saves with the 999 initial stack allocation. This happens in one of two ways: 1000 1001 (1) Using an STR or STP with writeback to perform the initial 1002 stack allocation. When EMIT_FRAME_CHAIN, the registers will 1003 be those needed to create a frame chain. 1004 1005 Indicated by CALLEE_ADJUST != 0. 1006 1007 (2) Using a separate STP to set up the frame record, after the 1008 initial stack allocation but before setting up the frame pointer. 1009 This is used if the offset is too large to use writeback. 1010 1011 Indicated by CALLEE_ADJUST == 0 && EMIT_FRAME_CHAIN. 1012 1013 These fields indicate which registers we've decided to handle using 1014 (1) or (2), or INVALID_REGNUM if none. 1015 1016 In some cases we don't always need to pop all registers in the push 1017 candidates, pop candidates record which registers need to be popped 1018 eventually. The initial value of a pop candidate is copied from its 1019 corresponding push candidate. 1020 1021 Currently, different pop candidates are only used for shadow call 1022 stack. When "-fsanitize=shadow-call-stack" is specified, we replace 1023 x30 in the pop candidate with INVALID_REGNUM to ensure that x30 is 1024 not popped twice. */ 1025 unsigned wb_push_candidate1; 1026 unsigned wb_push_candidate2; 1027 unsigned wb_pop_candidate1; 1028 unsigned wb_pop_candidate2; 1029 1030 /* Big-endian SVE frames need a spare predicate register in order 1031 to save vector registers in the correct layout for unwinding. 1032 This is the register they should use. */ 1033 unsigned spare_pred_reg; 1034 1035 /* An SVE register that is saved below the hard frame pointer and that acts 1036 as a probe for later allocations, or INVALID_REGNUM if none. */ 1037 unsigned sve_save_and_probe; 1038 1039 /* A register that is saved at the hard frame pointer and that acts 1040 as a probe for later allocations, or INVALID_REGNUM if none. */ 1041 unsigned hard_fp_save_and_probe; 1042 1043 bool laid_out; 1044 1045 /* True if shadow call stack should be enabled for the current function. */ 1046 bool is_scs_enabled; 1047 }; 1048 1049 #ifdef hash_set_h 1050 typedef struct GTY (()) machine_function 1051 { 1052 struct aarch64_frame frame; 1053 /* One entry for each hard register. */ 1054 bool reg_is_wrapped_separately[LAST_SAVED_REGNUM]; 1055 /* One entry for each general purpose register. */ 1056 rtx call_via[SP_REGNUM]; 1057 1058 /* A pseudo register that points to the function's TPIDR2 block, or null 1059 if the function doesn't have a TPIDR2 block. */ 1060 rtx tpidr2_block; 1061 1062 /* A pseudo register that points to the function's ZA save buffer, 1063 or null if none. */ 1064 rtx za_save_buffer; 1065 1066 /* A stack slot that stores the contents of the function's ZT0 state. */ 1067 rtx zt0_save_buffer; 1068 1069 bool label_is_assembled; 1070 1071 /* True if we've expanded at least one call to a function that changes 1072 PSTATE.SM. This should only be used for saving compile time: false 1073 guarantees that no such mode switch exists. */ 1074 bool call_switches_pstate_sm; 1075 1076 /* Used to generated unique identifiers for each update to ZA by an 1077 asm statement. */ 1078 unsigned int next_asm_update_za_id; 1079 1080 /* A set of all decls that have been passed to a vld1 intrinsic in the 1081 current function. This is used to help guide the vector cost model. */ 1082 hash_set<tree> *vector_load_decls; 1083 1084 /* An instruction that was emitted at the start of the function to 1085 set an Advanced SIMD pseudo register to zero. If the instruction 1086 still exists and still fulfils its original purpose. the same register 1087 can be reused by other code. */ 1088 rtx_insn *advsimd_zero_insn; 1089 } machine_function; 1090 #endif 1091 #endif 1092 1093 /* Which ABI to use. */ 1094 enum aarch64_abi_type 1095 { 1096 AARCH64_ABI_LP64 = 0, 1097 AARCH64_ABI_ILP32 = 1 1098 }; 1099 1100 #ifndef AARCH64_ABI_DEFAULT 1101 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 1102 #endif 1103 1104 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 1105 1106 enum arm_pcs 1107 { 1108 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 1109 ARM_PCS_SIMD, /* For aarch64_vector_pcs functions. */ 1110 ARM_PCS_SVE, /* For functions that pass or return 1111 values in SVE registers. */ 1112 ARM_PCS_TLSDESC, /* For targets of tlsdesc calls. */ 1113 ARM_PCS_UNKNOWN 1114 }; 1115 1116 1117 1118 1119 /* We can't use machine_mode inside a generator file because it 1120 hasn't been created yet; we shouldn't be using any code that 1121 needs the real definition though, so this ought to be safe. */ 1122 #ifdef GENERATOR_FILE 1123 #define MACHMODE int 1124 #else 1125 #include "insn-modes.h" 1126 #define MACHMODE machine_mode 1127 #endif 1128 1129 #ifndef USED_FOR_TARGET 1130 /* AAPCS related state tracking. */ 1131 typedef struct 1132 { 1133 enum arm_pcs pcs_variant; 1134 aarch64_feature_flags isa_mode; 1135 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1136 int aapcs_ncrn; /* Next Core register number. */ 1137 int aapcs_nextncrn; /* Next next core register number. */ 1138 int aapcs_nvrn; /* Next Vector register number. */ 1139 int aapcs_nextnvrn; /* Next Next Vector register number. */ 1140 int aapcs_nprn; /* Next Predicate register number. */ 1141 int aapcs_nextnprn; /* Next Next Predicate register number. */ 1142 rtx aapcs_reg; /* Register assigned to this argument. This 1143 is NULL_RTX if this parameter goes on 1144 the stack. */ 1145 MACHMODE aapcs_vfp_rmode; 1146 int aapcs_stack_words; /* If the argument is passed on the stack, this 1147 is the number of words needed, after rounding 1148 up. Only meaningful when 1149 aapcs_reg == NULL_RTX. */ 1150 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 1151 stack arg area so far. */ 1152 bool silent_p; /* True if we should act silently, rather than 1153 raise an error for invalid calls. */ 1154 1155 /* AARCH64_STATE_* flags that describe whether the function shares ZA 1156 and ZT0 with its callers. */ 1157 unsigned int shared_za_flags; 1158 unsigned int shared_zt0_flags; 1159 1160 /* A list of registers that need to be saved and restored around a 1161 change to PSTATE.SM. An auto_vec would be more convenient, but those 1162 can't be copied. */ 1163 unsigned int num_sme_mode_switch_args; 1164 rtx sme_mode_switch_args[12]; 1165 } CUMULATIVE_ARGS; 1166 #endif 1167 1168 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1169 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1170 1171 #define PAD_VARARGS_DOWN 0 1172 1173 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1174 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 1175 1176 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1177 aarch64_function_arg_regno_p(REGNO) 1178 1179 1181 /* ISA Features. */ 1182 1183 /* Addressing modes, etc. */ 1184 #define HAVE_POST_INCREMENT 1 1185 #define HAVE_PRE_INCREMENT 1 1186 #define HAVE_POST_DECREMENT 1 1187 #define HAVE_PRE_DECREMENT 1 1188 #define HAVE_POST_MODIFY_DISP 1 1189 #define HAVE_PRE_MODIFY_DISP 1 1190 1191 #define MAX_REGS_PER_ADDRESS 2 1192 1193 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 1194 1195 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1196 aarch64_regno_ok_for_base_p (REGNO, true) 1197 1198 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1199 aarch64_regno_ok_for_index_p (REGNO, true) 1200 1201 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1202 aarch64_legitimate_pic_operand_p (X) 1203 1204 #define CASE_VECTOR_MODE Pmode 1205 1206 #define DEFAULT_SIGNED_CHAR 0 1207 1208 /* An integer expression for the size in bits of the largest integer machine 1209 mode that should actually be used. We allow pairs of registers. */ 1210 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 1211 1212 /* Maximum bytes moved by a single instruction (load/store pair). */ 1213 #define MOVE_MAX (UNITS_PER_WORD * 2) 1214 1215 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 1216 #define AARCH64_CALL_RATIO 8 1217 1218 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 1219 move_by_pieces will continually copy the largest safe chunks. So a 1220 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 1221 for both size and speed of copy, so we will instead use the "cpymem" 1222 standard name to implement the copy. This logic does not apply when 1223 targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in 1224 that case. */ 1225 #define MOVE_RATIO(speed) \ 1226 ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 1227 1228 /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when 1229 we would use more than 3 scalar instructions. 1230 Otherwise follow a sensible default: when optimizing for size, give a better 1231 estimate of the length of a memset call, but use the default otherwise. */ 1232 #define CLEAR_RATIO(speed) \ 1233 (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO) 1234 1235 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant. Without 1236 -mstrict-align, make decisions in "setmem". Otherwise follow a sensible 1237 default: when optimizing for size adjust the ratio to account for the 1238 overhead of loading the constant. */ 1239 #define SET_RATIO(speed) \ 1240 ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2) 1241 1242 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 1243 rarely a good idea in straight-line code since it adds an extra address 1244 dependency between each instruction. Better to use incrementing offsets. */ 1245 #define USE_LOAD_POST_INCREMENT(MODE) 0 1246 #define USE_LOAD_POST_DECREMENT(MODE) 0 1247 #define USE_LOAD_PRE_INCREMENT(MODE) 0 1248 #define USE_LOAD_PRE_DECREMENT(MODE) 0 1249 #define USE_STORE_POST_INCREMENT(MODE) 0 1250 #define USE_STORE_POST_DECREMENT(MODE) 0 1251 #define USE_STORE_PRE_INCREMENT(MODE) 0 1252 #define USE_STORE_PRE_DECREMENT(MODE) 0 1253 1254 /* WORD_REGISTER_OPERATIONS does not hold for AArch64. 1255 The assigned word_mode is DImode but operations narrower than SImode 1256 behave as 32-bit operations if using the W-form of the registers rather 1257 than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS 1258 expects. */ 1259 #define WORD_REGISTER_OPERATIONS 0 1260 1261 /* Define if loading from memory in MODE, an integral mode narrower than 1262 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 1263 macro should be the code that says which one of the two operations is 1264 implicitly done, or UNKNOWN if none. */ 1265 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1266 1267 /* Define this macro to be non-zero if instructions will fail to work 1268 if given data not on the nominal alignment. */ 1269 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 1270 1271 /* Enable wide bitfield accesses for more efficient bitfield code. */ 1272 #define SLOW_BYTE_ACCESS 1 1273 1274 #define NO_FUNCTION_CSE 1 1275 1276 /* Specify the machine mode that the hardware addresses have. 1277 After generation of rtl, the compiler makes no further distinction 1278 between pointers and any other objects of this machine mode. */ 1279 #define Pmode DImode 1280 1281 /* A C expression whose value is zero if pointers that need to be extended 1282 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1283 greater then zero if they are zero-extended and less then zero if the 1284 ptr_extend instruction should be used. */ 1285 #define POINTERS_EXTEND_UNSIGNED 1 1286 1287 /* Mode of a function address in a call instruction (for indexing purposes). */ 1288 #define FUNCTION_MODE Pmode 1289 1290 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 1291 1292 /* Having an integer comparison mode guarantees that we can use 1293 reverse_condition, but the usual restrictions apply to floating-point 1294 comparisons. */ 1295 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode) 1296 1297 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1298 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1299 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1300 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 1301 1302 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 1303 1304 #define RETURN_ADDR_RTX aarch64_return_addr 1305 1306 /* BTI c + 3 insns 1307 + sls barrier of DSB + ISB. 1308 + 2 pointer-sized entries. */ 1309 #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16)) 1310 1311 /* Trampolines contain dwords, so must be dword aligned. */ 1312 #define TRAMPOLINE_ALIGNMENT 64 1313 1314 /* Put trampolines in the text section so that mapping symbols work 1315 correctly. */ 1316 #define TRAMPOLINE_SECTION text_section 1317 1318 /* To start with. */ 1319 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1320 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 1321 1322 1324 /* Assembly output. */ 1325 1326 /* For now we'll make all jump tables pc-relative. */ 1327 #define CASE_VECTOR_PC_RELATIVE 1 1328 1329 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1330 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 1331 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 1332 : QImode) 1333 1334 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 1335 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 1336 1337 #define MCOUNT_NAME "_mcount" 1338 1339 #define NO_PROFILE_COUNTERS 1 1340 1341 /* Emit rtl for profiling. Output assembler code to FILE 1342 to call "_mcount" for profiling a function entry. */ 1343 #define PROFILE_HOOK(LABEL) \ 1344 { \ 1345 rtx fun, lr; \ 1346 lr = aarch64_return_addr_rtx (); \ 1347 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 1348 emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode); \ 1349 } 1350 1351 /* All the work done in PROFILE_HOOK, but still required. */ 1352 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 1353 1354 /* For some reason, the Linux headers think they know how to define 1355 these macros. They don't!!! */ 1356 #undef ASM_APP_ON 1357 #undef ASM_APP_OFF 1358 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 1359 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 1360 1361 #define CONSTANT_POOL_BEFORE_FUNCTION 0 1362 1363 /* This definition should be relocated to aarch64-elf-raw.h. This macro 1364 should be undefined in aarch64-linux.h and a clear_cache pattern 1365 implmented to emit either the call to __aarch64_sync_cache_range() 1366 directly or preferably the appropriate sycall or cache clear 1367 instructions inline. */ 1368 #define CLEAR_INSN_CACHE(beg, end) \ 1369 extern void __aarch64_sync_cache_range (void *, void *); \ 1370 __aarch64_sync_cache_range (beg, end) 1371 1372 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) 1373 1374 /* Choose appropriate mode for caller saves, so we do the minimum 1375 required size of load/store. */ 1376 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1377 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 1378 1379 #undef SWITCHABLE_TARGET 1380 #define SWITCHABLE_TARGET 1 1381 1382 /* Check TLS Descriptors mechanism is selected. */ 1383 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 1384 1385 extern enum aarch64_code_model aarch64_cmodel; 1386 1387 /* When using the tiny addressing model conditional and unconditional branches 1388 can span the whole of the available address space (1MB). */ 1389 #define HAS_LONG_COND_BRANCH \ 1390 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1391 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1392 1393 #define HAS_LONG_UNCOND_BRANCH \ 1394 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 1395 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 1396 1397 #define TARGET_HAS_FMV_TARGET_ATTRIBUTE 0 1398 1399 #define TARGET_SUPPORTS_WIDE_INT 1 1400 1401 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 1402 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 1403 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1404 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 1405 || (MODE) == DFmode || (MODE) == V4BFmode) 1406 1407 /* Modes valid for AdvSIMD Q registers. */ 1408 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 1409 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1410 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 1411 || (MODE) == V2DFmode || (MODE) == V8BFmode) 1412 1413 #define ENDIAN_LANE_N(NUNITS, N) \ 1414 (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) 1415 1416 /* Extra specs when building a native AArch64-hosted compiler. 1417 Option rewriting rules based on host system. */ 1418 #if defined(__aarch64__) && \ 1419 (defined(__linux__) || defined(__NetBSD__)) 1420 extern const char *host_detect_local_cpu (int argc, const char **argv); 1421 #define HAVE_LOCAL_CPU_DETECT 1422 # define EXTRA_SPEC_FUNCTIONS \ 1423 { "local_cpu_detect", host_detect_local_cpu }, \ 1424 MCPU_TO_MARCH_SPEC_FUNCTIONS 1425 1426 /* Rewrite -m{arch,cpu,tune}=native based on the host system information. 1427 When rewriting -march=native convert it into an -mcpu option if no other 1428 -mcpu or -mtune was given. */ 1429 # define MCPU_MTUNE_NATIVE_SPECS \ 1430 " %{march=native:%<march=native %:local_cpu_detect(%{mcpu=*|mtune=*:arch;:cpu})}" \ 1431 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 1432 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 1433 /* This will be used in OPTION_DEFAULT_SPECS below. 1434 When GCC is configured with --with-tune we don't want to materialize an 1435 implicit -mtune would prevent the rewriting of -march=native into 1436 -mcpu=native as per the above rules. */ 1437 #define CONFIG_TUNE_SPEC \ 1438 { "tune", "%{!mcpu=*:%{!mtune=*:%{!march=native:-mtune=%(VALUE)}}}" }, 1439 #else 1440 # define MCPU_MTUNE_NATIVE_SPECS "" 1441 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 1442 # define CONFIG_TUNE_SPEC \ 1443 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, 1444 #endif 1445 1446 /* Support for configure-time --with-arch, --with-cpu and --with-tune. 1447 --with-arch and --with-cpu are ignored if either -mcpu or -march is used. 1448 --with-tune is ignored if either -mtune or -mcpu is used (but is not 1449 affected by -march, except in the -march=native case as per the 1450 CONFIG_TUNE_SPEC above). */ 1451 #define OPTION_DEFAULT_SPECS \ 1452 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 1453 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 1454 CONFIG_TUNE_SPEC 1455 1456 #define MCPU_TO_MARCH_SPEC \ 1457 "%{!march=*:%{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}}" 1458 1459 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 1460 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 1461 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 1462 1463 #define ASM_CPU_SPEC \ 1464 MCPU_TO_MARCH_SPEC 1465 1466 #define EXTRA_SPECS \ 1467 { "asm_cpu_spec", ASM_CPU_SPEC } 1468 1469 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 1470 1471 /* This type is the user-visible __fp16, and a pointer to that type. We 1472 need it in many places in the backend. Defined in aarch64-builtins.cc. */ 1473 extern GTY(()) tree aarch64_fp16_type_node; 1474 extern GTY(()) tree aarch64_fp16_ptr_type_node; 1475 1476 /* Pointer to the user-visible __bf16 type. __bf16 itself is generic 1477 bfloat16_type_node. Defined in aarch64-builtins.cc. */ 1478 extern GTY(()) tree aarch64_bf16_ptr_type_node; 1479 1480 /* The generic unwind code in libgcc does not initialize the frame pointer. 1481 So in order to unwind a function using a frame pointer, the very first 1482 function that is unwound must save the frame pointer. That way the frame 1483 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 1484 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 1485 #define LIBGCC2_UNWIND_ATTRIBUTE \ 1486 __attribute__((optimize ("no-omit-frame-pointer"))) 1487 1488 #ifndef USED_FOR_TARGET 1489 extern poly_uint16 aarch64_sve_vg; 1490 1491 /* The number of bits and bytes in an SVE vector. */ 1492 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64)) 1493 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8)) 1494 1495 /* The number of bits and bytes in an SVE predicate. */ 1496 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR 1497 #define BYTES_PER_SVE_PRED aarch64_sve_vg 1498 1499 /* The SVE mode for a vector of bytes. */ 1500 #define SVE_BYTE_MODE VNx16QImode 1501 1502 /* The maximum number of bytes in a fixed-size vector. This is 256 bytes 1503 (for -msve-vector-bits=2048) multiplied by the maximum number of 1504 vectors in a structure mode (4). 1505 1506 This limit must not be used for variable-size vectors, since 1507 VL-agnostic code must work with arbitary vector lengths. */ 1508 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4) 1509 #endif 1510 1511 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE) 1512 1513 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the 1514 outgoing arguments if stack clash protection is enabled. This is essential 1515 as the extra arg space allows us to skip a check in alloca. */ 1516 #undef STACK_DYNAMIC_OFFSET 1517 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1518 ((flag_stack_clash_protection \ 1519 && cfun->calls_alloca \ 1520 && known_lt (crtl->outgoing_args_size, \ 1521 STACK_CLASH_MIN_BYTES_OUTGOING_ARGS)) \ 1522 ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS, \ 1523 STACK_BOUNDARY / BITS_PER_UNIT) \ 1524 : (crtl->outgoing_args_size + STACK_POINTER_OFFSET)) 1525 1526 /* Filled in by aarch64_adjust_reg_alloc_order, which is called before 1527 the first relevant use. */ 1528 #define REG_ALLOC_ORDER {} 1529 #define ADJUST_REG_ALLOC_ORDER aarch64_adjust_reg_alloc_order () 1530 1531 #define AARCH64_VALID_SHRN_OP(T,S) \ 1532 ((T) == TRUNCATE \ 1533 || ((T) == US_TRUNCATE && (S) == LSHIFTRT) \ 1534 || ((T) == SS_TRUNCATE && (S) == ASHIFTRT)) 1535 1536 #ifndef USED_FOR_TARGET 1537 1538 /* Enumerates the mode-switching "entities" for AArch64. */ 1539 enum class aarch64_mode_entity : int 1540 { 1541 /* An aarch64_tristate_mode that says whether we have created a local 1542 save buffer for the current function's ZA state. The only transition 1543 is from NO to YES. */ 1544 HAVE_ZA_SAVE_BUFFER, 1545 1546 /* An aarch64_local_sme_state that reflects the state of all data 1547 controlled by PSTATE.ZA. */ 1548 LOCAL_SME_STATE 1549 }; 1550 1551 /* Describes the state of all data controlled by PSTATE.ZA */ 1552 enum class aarch64_local_sme_state : int 1553 { 1554 /* ZA is in the off or dormant state. If it is dormant, the contents 1555 of ZA belong to a caller. */ 1556 INACTIVE_CALLER, 1557 1558 /* ZA is in the off state: PSTATE.ZA is 0 and TPIDR2_EL0 is null. */ 1559 OFF, 1560 1561 /* ZA is in the off or dormant state. If it is dormant, the contents 1562 of ZA belong to the current function. */ 1563 INACTIVE_LOCAL, 1564 1565 /* ZA is in the off state and the current function's ZA contents are 1566 stored in the lazy save buffer. This is the state on entry to 1567 exception handlers. */ 1568 SAVED_LOCAL, 1569 1570 /* ZA is in the active state: PSTATE.ZA is 1 and TPIDR2_EL0 is null. 1571 The contents of ZA are live. */ 1572 ACTIVE_LIVE, 1573 1574 /* ZA is in the active state: PSTATE.ZA is 1 and TPIDR2_EL0 is null. 1575 The contents of ZA are dead. */ 1576 ACTIVE_DEAD, 1577 1578 /* ZA could be in multiple states. */ 1579 ANY 1580 }; 1581 1582 enum class aarch64_tristate_mode : int { NO, YES, MAYBE }; 1583 1584 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 1585 aarch64_optimize_mode_switching (aarch64_mode_entity (ENTITY)) 1586 1587 #define NUM_MODES_FOR_MODE_SWITCHING \ 1588 { int (aarch64_tristate_mode::MAYBE), \ 1589 int (aarch64_local_sme_state::ANY) } 1590 1591 #endif 1592 1593 #endif /* GCC_AARCH64_H */ 1594
Indexes created Wed Jul 15 00:26:21 UTC 2026