| /src/sys/external/bsd/gnu-efi/dist/inc/aarch64/ |
| efisetjmp_arch.h | 31 UINT64 D14;
|
| /src/crypto/external/apache2/openssl/dist/crypto/sha/asm/ |
| keccak1600-avx2.pl | 126 my ($C14,$C00,$D00,$D14) = @T[5..8];
157 vpermq \$0b00111001,@T[1],$D14
171 vpblendd \$0b11000000,@T[1],$D14,$D14
173 vpxor @T[4],$D14,$D14 # D[1..4] = ROL64(C[2..4,0),1) ^ C[0..3]
180 vpxor $D14,$A31,$A31 # ^= D[1..4] from Theta
185 vpxor $D14,$A21,$A21 # ^= D[1..4] from Theta
190 vpxor $D14,$A41,$A41 # ^= D[1..4] from Theta
195 vpxor $D14,$A11,$A11 # ^= D[1..4] from Thet
[all...] |
| keccak1600-avx512vl.pl | 55 my ($C14,$C00,$D00,$D14) = @T[5..8];
82 vpermq \$0b00111001,@T[1],$D14
91 vpblendd \$0b11000000,@T[1],$D14,$D14
98 vpternlogq \$0x96,@T[0],$D14,$A31 # ^= D[1..4] from Theta
101 vpternlogq \$0x96,@T[0],$D14,$A21 # ^= D[1..4] from Theta
104 vpternlogq \$0x96,@T[0],$D14,$A41 # ^= D[1..4] from Theta
109 vpternlogq \$0x96,@T[0],$D14,$A11 # ^= D[1..4] from Theta
114 vpternlogq \$0x96,@T[0],$D14,$A01 # ^= D[1..4] from Theta
|
| /src/crypto/external/bsd/openssl/dist/crypto/sha/asm/ |
| keccak1600-avx2.pl | 126 my ($C14,$C00,$D00,$D14) = @T[5..8];
157 vpermq \$0b00111001,@T[1],$D14
171 vpblendd \$0b11000000,@T[1],$D14,$D14
173 vpxor @T[4],$D14,$D14 # D[1..4] = ROL64(C[2..4,0),1) ^ C[0..3]
180 vpxor $D14,$A31,$A31 # ^= D[1..4] from Theta
185 vpxor $D14,$A21,$A21 # ^= D[1..4] from Theta
190 vpxor $D14,$A41,$A41 # ^= D[1..4] from Theta
195 vpxor $D14,$A11,$A11 # ^= D[1..4] from Thet
[all...] |
| keccak1600-avx512vl.pl | 55 my ($C14,$C00,$D00,$D14) = @T[5..8];
82 vpermq \$0b00111001,@T[1],$D14
91 vpblendd \$0b11000000,@T[1],$D14,$D14
98 vpternlogq \$0x96,@T[0],$D14,$A31 # ^= D[1..4] from Theta
101 vpternlogq \$0x96,@T[0],$D14,$A21 # ^= D[1..4] from Theta
104 vpternlogq \$0x96,@T[0],$D14,$A41 # ^= D[1..4] from Theta
109 vpternlogq \$0x96,@T[0],$D14,$A11 # ^= D[1..4] from Theta
114 vpternlogq \$0x96,@T[0],$D14,$A01 # ^= D[1..4] from Theta
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/ |
| keccak1600-avx2.pl | 126 my ($C14,$C00,$D00,$D14) = @T[5..8];
157 vpermq \$0b00111001,@T[1],$D14
171 vpblendd \$0b11000000,@T[1],$D14,$D14
173 vpxor @T[4],$D14,$D14 # D[1..4] = ROL64(C[2..4,0),1) ^ C[0..3]
180 vpxor $D14,$A31,$A31 # ^= D[1..4] from Theta
185 vpxor $D14,$A21,$A21 # ^= D[1..4] from Theta
190 vpxor $D14,$A41,$A41 # ^= D[1..4] from Theta
195 vpxor $D14,$A11,$A11 # ^= D[1..4] from Thet
[all...] |
| keccak1600-avx512vl.pl | 55 my ($C14,$C00,$D00,$D14) = @T[5..8];
82 vpermq \$0b00111001,@T[1],$D14
91 vpblendd \$0b11000000,@T[1],$D14,$D14
98 vpternlogq \$0x96,@T[0],$D14,$A31 # ^= D[1..4] from Theta
101 vpternlogq \$0x96,@T[0],$D14,$A21 # ^= D[1..4] from Theta
104 vpternlogq \$0x96,@T[0],$D14,$A41 # ^= D[1..4] from Theta
109 vpternlogq \$0x96,@T[0],$D14,$A11 # ^= D[1..4] from Theta
114 vpternlogq \$0x96,@T[0],$D14,$A01 # ^= D[1..4] from Theta
|
| /src/external/bsd/pcc/dist/pcc/arch/sparc64/ |
| macdefs.h | 199 #define D14 76
247 { D14, -1 }, { D14, -1 }, { D15, -1 }, /* { D15, -1 }, */ \
|
| /src/lib/libm/ld128/ |
| s_expl.c | 193 D14 = 1.1470726176204336e-11, /* 0x1.93971dc395d9ep-37 */
252 dx * (D14 + dx * (D15 + dx * (D16 +
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 78 case D15: case D14: case D13: case D12:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 125 case AArch64::D14: return AArch64::B14;
165 case AArch64::B14: return AArch64::D14;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 119 case AArch64::D14:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 675 // D14/D15 pair = 0x00000800
685 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
|
| AArch64MCTargetDesc.cpp | 181 {codeview::RegisterId::ARM64_D14, AArch64::D14},
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 288 {codeview::RegisterId::ARM_ND14, ARM::D14},
|
| ARMAsmBackend.cpp | 1266 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 595 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 88 SP::D14, SP::D30, SP::D15, SP::D31 };
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 159 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 351 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 5936 if (parseRegisterInRange(Reg, AArch64::D0, AArch64::D8, AArch64::D14) ||
5948 if (parseRegisterInRange(Reg, AArch64::D0, AArch64::D8, AArch64::D14) ||
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 315 .Case("r29:28", Hexagon::D14)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 1340 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 3273 case Mips::D14: return Mips::F29;
|
