| /src/sys/external/bsd/gnu-efi/dist/inc/arm/ |
| efisetjmp_arch.h | 17 UINT32 R11;
|
| /src/sys/arch/vax/boot/boot/ |
| consio2.S | 64 ENTRY(ka630_rom_getchar, 0x0802) # save-mask: R1, R11
65 movl _C_LABEL(ka630_conspage),%r11 # load location of console page
67 jsb *0x1C(%r11) # call the getc-routine (KA630_GETC)
82 ENTRY(ka630_rom_putchar, 0x802) # save-mask: R1, R11
83 movl _C_LABEL(ka630_conspage),%r11
86 jsb *0x20(%r11) # is rom ready? (KA630_PUTC_POLL)
89 jsb *0x24(%r11) # output character (KA630_PUTC)
95 ENTRY(ka53_rom_getchar, 0x0802) # save-mask: R1, R11
96 movl _C_LABEL(ka53_conspage),%r11
99 jsb *0x64(%r11) # test for cha
[all...] |
| /src/external/gpl3/gcc/dist/libgcc/config/msp430/ |
| slli.S | 128 /* Logical Left Shift - R8:R11 -> R12:R15
130 special conventions, so the 64-bit value to shift is passed in R8:R11.
137 MOV R11, R15 ; Free up R11 first
138 MOV R12, R11 ; Save the shift amount in R11
142 CMP #0,R11
154 ADD #-1,R11
|
| srai.S | 127 /* Arithmetic Right Shift - R8:R11 -> R12:R15
129 special conventions, so the 64-bit value to shift is passed in R8:R11.
136 MOV R11, R15 ; Free up R11 first
137 MOV R12, R11 ; Save the shift amount in R11
141 CMP #0, R11
153 ADD #-1,R11
|
| srli.S | 132 /* Logical Right Shift - R8:R11 -> R12:R15
134 special conventions, so the 64-bit value to shift is passed in R8:R11.
141 MOV R11, R15 ; Free up R11 first
142 MOV R12, R11 ; Save the shift amount in R11
146 CMP #0,R11
159 ADD #-1,R11
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/msp430/ |
| slli.S | 128 /* Logical Left Shift - R8:R11 -> R12:R15
130 special conventions, so the 64-bit value to shift is passed in R8:R11.
137 MOV R11, R15 ; Free up R11 first
138 MOV R12, R11 ; Save the shift amount in R11
142 CMP #0,R11
154 ADD #-1,R11
|
| srai.S | 127 /* Arithmetic Right Shift - R8:R11 -> R12:R15
129 special conventions, so the 64-bit value to shift is passed in R8:R11.
136 MOV R11, R15 ; Free up R11 first
137 MOV R12, R11 ; Save the shift amount in R11
141 CMP #0, R11
153 ADD #-1,R11
|
| srli.S | 132 /* Logical Right Shift - R8:R11 -> R12:R15
134 special conventions, so the 64-bit value to shift is passed in R8:R11.
141 MOV R11, R15 ; Free up R11 first
142 MOV R12, R11 ; Save the shift amount in R11
146 CMP #0,R11
159 ADD #-1,R11
|
| /src/sys/arch/amd64/include/ |
| frame_regs.h | 43 greg(r11, R11, 7) /* tf_r11 */ \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiBaseInfo.h | 69 case Lanai::R11:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
| /src/external/bsd/pcc/dist/pcc/arch/vax/ |
| macdefs.h | 137 # define R11 11
226 { R10, R11, XR9, -1 },
|
| /src/external/gpl3/gdb/dist/gdbserver/ |
| netbsd-amd64-low.cc | 43 AMD64_R11_REGNUM, /* %r11 */
107 netbsd_x86_64_collect_gp (AMD64_R11_REGNUM, R11);
144 netbsd_x86_64_supply_gp (AMD64_R11_REGNUM, R11);
|
| /src/external/gpl3/gdb.old/dist/gdbserver/ |
| netbsd-amd64-low.cc | 43 AMD64_R11_REGNUM, /* %r11 */
105 netbsd_x86_64_collect_gp (AMD64_R11_REGNUM, R11);
142 netbsd_x86_64_supply_gp (AMD64_R11_REGNUM, R11);
|
| /src/external/gpl3/gdb/dist/gdb/ |
| amd64-windows-nat.c | 38 context_offset (R11),
|
| /src/external/gpl3/gdb.old/dist/gdb/ |
| amd64-windows-nat.c | 38 context_offset (R11),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86IndirectThunks.cpp | 90 // jmpq *%r11
92 // This ensures that if the value in register %r11 was loaded from memory,
93 // then the value in %r11 is (architecturally) correct prior to the jump.
96 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11);
97 MF.front().addLiveIn(X86::R11);
148 "Should only have an r11 thunk on 64-bit targets");
158 // movq %r11, (%rsp)
160 ThunkReg = X86::R11;
|
| /src/external/bsd/pcc/dist/pcc/arch/pdp10/ |
| macdefs.h | 170 #define R11 011
229 { R10, R11, XR7, XR11, -1 }, \
230 { R11, R12, XR10, XR12, -1 }, \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCTargetDesc.cpp | 43 InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
|
| /src/external/gpl3/gcc/dist/libgcc/config/rl78/ |
| fpbit-sf.S | 30 ;; Output to R8..R11.
272 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb).
292 ;; Load the value into r10:r11:X:A
316 mov a, r11
331 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb)
342 ;; Input in (lsb) r10.r11.x.a (msb).
349 ;; A X R11 R10
353 ;; A X R11 R10
368 or a, r11
402 ;; H X R11 R1
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/rl78/ |
| fpbit-sf.S | 30 ;; Output to R8..R11.
272 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb).
292 ;; Load the value into r10:r11:X:A
316 mov a, r11
331 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb)
342 ;; Input in (lsb) r10.r11.x.a (msb).
349 ;; A X R11 R10
353 ;; A X R11 R10
368 or a, r11
402 ;; H X R11 R1
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 54 case R8: case R9: case R10: case R11: case R12:
66 case R8: case R9: case R10: case R11: case R12:
|
| /src/external/bsd/pcc/dist/pcc/arch/arm/ |
| macdefs.h | 127 #define R11 11
134 #define FP R11
|
| /src/external/bsd/pcc/dist/pcc/arch/hppa/ |
| macdefs.h | 128 #define R11 11
168 #define RD17 49 /* r11:r10 */
169 #define RD18 50 /* r12:r11 */
364 { R11, R10, -1 }, \
365 { R12, R11, -1 }, \
|
| /src/sys/arch/vax/include/ |
| asm.h | 47 #define R11 0x800
|
