| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiBaseInfo.h | 111 case Lanai::R31:
|
| /src/external/bsd/pcc/dist/pcc/arch/hppa/ |
| macdefs.h | 148 #define R31 31
152 #define RD1 33 /* r1:r31 */
157 #define RD6 38 /* r31:t4 */
158 #define RD7 39 /* r31:t3 */
159 #define RD8 40 /* r31:t2 */
160 #define RD9 41 /* r31:t1 */
348 { R1, R31, -1 }, \
353 { R31, T4, -1 }, \
354 { R31, T3, -1 }, \
355 { R31, T2, -1 },
[all...] |
| local2.c | 46 { R0, R1, R1, R1, R1, R1, R31, R31, R31, R31,
50 { R0, R31, T4, T3, T2, T1, T4, T3, T2, T1,
89 if (i <= R31)
160 if (i <= R31)
757 "%ret0", "%ret1", "%sp", "%r31",
|
| /src/external/bsd/pcc/dist/pcc/arch/powerpc/ |
| macdefs.h | 178 #define R31 31
265 SAREG, /* R31 */ \
327 { R30, R31, -1 }, \
342 #define GOTREG R31 /* global offset table (PIC) */
|
| local2.c | 61 REGPREFIX "r30", REGPREFIX "r31",
130 /* save registers R30 and R31 */
648 printf("%s,ha16(", rnames[R31]);
664 printf("%s," LABFMT "@ha\n", rnames[R31], lab);
672 printf("%s,ha16(", rnames[R31]);
750 printf("%s,ha16(", rnames[R31]);
766 printf("%s," LABFMT "@ha\n", rnames[R31], lab);
774 printf("%s,ha16(", rnames[R31]);
1255 p2framesize += 8; /* for R31 and R30 */
|
| order.c | 385 static int r[] = { R10, R9, R8, R7, R6, R5, R4, R3, R30, R31, -1 };
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| cpustate.h | 73 R31,
76 SP = R31,
77 ZR = R31
|
| cpustate.c | 37 For others a read from r31 always returns 0, and a write to r31 is ignored. */
38 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
45 if (reg == R31 && ! r31_is_sp)
64 if (reg == R31 && ! r31_is_sp)
107 if (reg == R31 && ! r31_is_sp)
132 if (reg == R31 && ! r31_is_sp)
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 73 R31,
76 SP = R31,
77 ZR = R31
|
| cpustate.c | 37 For others a read from r31 always returns 0, and a write to r31 is ignored. */
38 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
45 if (reg == R31 && ! r31_is_sp)
64 if (reg == R31 && ! r31_is_sp)
107 if (reg == R31 && ! r31_is_sp)
132 if (reg == R31 && ! r31_is_sp)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 57 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
152 Reserved.set(Hexagon::R31);
397 return Hexagon::R31;
|
| /src/crypto/external/apache2/openssl/dist/crypto/sha/asm/ |
| keccak1600-avx512vl.pl | 56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
99 vprolvq $R31,$A31,$A31
212 vmovdqa64 2*32(%r8),$R31
298 vmovdqa64 2*32(%r8),$R31
|
| /src/crypto/external/bsd/openssl/dist/crypto/sha/asm/ |
| keccak1600-avx512vl.pl | 56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
99 vprolvq $R31,$A31,$A31
212 vmovdqa64 2*32(%r8),$R31
298 vmovdqa64 2*32(%r8),$R31
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/ |
| keccak1600-avx512vl.pl | 56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
99 vprolvq $R31,$A31,$A31
212 vmovdqa64 2*32(%r8),$R31
298 vmovdqa64 2*32(%r8),$R31
|
| /src/external/gpl3/gcc/dist/libgcc/config/avr/libf7/ |
| asm-defs.h | 93 to move R25:R24 to R31:R30, i.e. plain register numbers
108 r30, r31
124 R30, R31
169 ldi r31, hi8(gs(.L_prologue_saves.\@)) variable
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/avr/libf7/ |
| asm-defs.h | 93 to move R25:R24 to R31:R30, i.e. plain register numbers
108 r30, r31
124 R30, R31
169 ldi r31, hi8(gs(.L_prologue_saves.\@)) variable
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 161 Lanai::R30, Lanai::R31};
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 236 // [if ([!]p0[.new])] jumpr r31
276 // jumpr r31
277 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0.
279 if (Hexagon::R31 == DstReg)
297 // [if ([!]p0[.new])] jumpr r31
298 if ((Hexagon::P0 == SrcReg) && (Hexagon::R31 == DstReg)) {
630 // If jumpr r31 appears, it must be in slot 0, and never slot 1 (MIb).
633 (MIb.getOperand(1).getReg() == Hexagon::R31))
636 (MIb.getOperand(0).getReg() == Hexagon::R31))
827 break; // none SUBInst jumpr r31
[all...] |
| HexagonMCTargetDesc.cpp | 288 InitHexagonMCRegisterInfo(X, Hexagon::R31);
|
| HexagonMCChecker.cpp | 106 if (Hexagon::R31 != R && MCID.isCall())
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/ |
| AVRDisassembler.cpp | 68 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 333 markSuperRegs(Reserved, PPC::R31);
654 .addReg(PPC::R31)
1367 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
|
| PPCFrameLowering.cpp | 119 {PPC::R31, -4}, \
386 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
587 // a copy of r1 into r31 and that makes keeping track of updates to r1 more
650 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1153 // If there is a frame pointer, copy R1 into R31
1563 Register FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1651 // to restore from the stack frame (e.g. R31). If the frame size is not
1710 // value of R31 in this case. Similar situation exists with setjmp.
1973 // Save R31 if necessary
2004 // Make sure we don't explicitly spill r31, because, for example, we hav
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/inc/ |
| efidebug.h | 359 UINT64 R31;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 554 Hexagon::R30, Hexagon::R31};
|
