| /src/crypto/external/apache2/openssl/dist/crypto/sha/asm/ |
| sha256-riscv64-zvkb-zvknha_or_zvknhb.pl | 66 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
156 @{[vmv_v_v $V30, $V6]}
281 @{[vadd_vv $V6, $V30, $V6]}
|
| sha512-riscv64-zvkb-zvknhb.pl | 66 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
|
| /src/crypto/external/apache2/openssl/dist/crypto/chacha/asm/ |
| chacha-riscv64-v-zbb.pl | 94 $V22, $V23, $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
458 @{[vxor_vv $V30, $V30, $V14]}
|
| /src/crypto/external/apache2/openssl/dist/crypto/sm3/asm/ |
| sm3-riscv64-zvksh.pl | 70 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| cpustate.h | 122 V30,
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 122 V30,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.cpp | 110 SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
|
| /src/crypto/external/apache2/openssl/dist/crypto/aes/asm/ |
| aes-riscv64-zvkb-zvkned.pl | 77 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
|
| aes-riscv64-zvbb-zvkg-zvkned.pl | 79 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
|
| aes-riscv64-zvkned.pl | 64 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 83 V28, V29, V30, V31, 0
|
| /src/crypto/external/apache2/openssl/dist/crypto/modes/asm/ |
| aes-gcm-riscv64-zvkb-zvkg-zvkned.pl | 92 $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 583 Hexagon::V30, Hexagon::V31};
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/ |
| VEDisassembler.cpp | 102 VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 162 {PPC::V30, -32}, \
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 8193 .Case("{v30}", RISCV::V30)
|
