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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
cli-sti.s 1 # Blackfin testcase for cli/sti instructions
compare.s 1 # Blackfin testcase for compare instructions
link-2.s 1 # Blackfin testcase for link/unlink instructions
events.s 8 # Run enough instructions to trigger event processing
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
cli-sti.s 1 # Blackfin testcase for cli/sti instructions
compare.s 1 # Blackfin testcase for compare instructions
link-2.s 1 # Blackfin testcase for link/unlink instructions
events.s 8 # Run enough instructions to trigger event processing
  /src/external/apache2/llvm/dist/llvm/bindings/python/llvm/tests/
test_disassembler.py 30 instructions = list(disassembler.get_instructions(sequence))
31 self.assertEqual(len(instructions), 2)
33 self.assertEqual(instructions[0], (0, 3, '\tjcxz\t-127'))
34 self.assertEqual(instructions[1], (3, 2, '\taddl\t%eax, %edi'))
  /src/external/ibm-public/postfix/dist/
Makefile 19 @echo Please review the INSTALL instructions first.
  /src/external/gpl3/gdb/dist/sim/ppc/
gen-icache.h 62 (insn_table *instructions,
67 /* Output a single instructions decoder */
igen.c 351 insn_table *instructions = NULL; local
362 printf(" -F <filter-out-flag> eg -F 64 to skip 64bit instructions\n");
497 instructions = load_insn_table(optarg, decode_rules, filters, includes,
500 insn_table_expand_insns(instructions);
525 ASSERT(instructions != NULL);
529 gen_semantics_h(instructions, file, code);
531 gen_semantics_c(instructions, cache_rules, file, code);
535 gen_idecode_h(file, instructions, cache_rules);
537 gen_idecode_c(file, instructions, cache_rules);
541 gen_model_h(instructions, file)
    [all...]
  /src/external/gpl3/gdb/dist/sim/testsuite/mips/
r6-removed.s 1 # Tests the instructions removed in R6 are correctly invalidated
  /src/external/gpl3/gdb.old/dist/sim/ppc/
gen-icache.h 62 (insn_table *instructions,
67 /* Output a single instructions decoder */
igen.c 351 insn_table *instructions = NULL; local
362 printf(" -F <filter-out-flag> eg -F 64 to skip 64bit instructions\n");
497 instructions = load_insn_table(optarg, decode_rules, filters, includes,
500 insn_table_expand_insns(instructions);
525 ASSERT(instructions != NULL);
529 gen_semantics_h(instructions, file, code);
531 gen_semantics_c(instructions, cache_rules, file, code);
535 gen_idecode_h(file, instructions, cache_rules);
537 gen_idecode_c(file, instructions, cache_rules);
541 gen_model_h(instructions, file)
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/testsuite/mips/
r6-removed.s 1 # Tests the instructions removed in R6 are correctly invalidated
  /src/sys/arch/arm/xscale/
ixp425-fw.mk 9 # See ixp425-fw.README for instructions on how to download and generate
  /src/external/bsd/am-utils/dist/
cvs-server.txt 2 Here are generic CVS server instructions:
  /src/external/gpl3/gdb/dist/sim/testsuite/riscv/
m-ext.s 1 # Check that the RV32M instructions run without any faults.
  /src/external/gpl3/gdb.old/dist/sim/testsuite/riscv/
m-ext.s 1 # Check that the RV32M instructions run without any faults.
  /src/games/cribbage/
instr.c 59 instructions(void) function
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
InstIterator.h 10 // instructions in a function. This is effectively a wrapper around a two level
14 // instructions are moved around.
133 inline inst_range instructions(Function *F) { function in namespace:llvm
142 inline const_inst_range instructions(const Function *F) { function in namespace:llvm
147 inline inst_range instructions(Function &F) { function in namespace:llvm
156 inline const_inst_range instructions(const Function &F) { function in namespace:llvm
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXAtomicLower.cpp 19 #include "llvm/IR/Instructions.h"
26 // Hoisting the alloca instructions in the non-entry blocks to the entry
47 for (Instruction &I : instructions(F))
  /src/external/gpl3/gdb/dist/sim/igen/
gen-icache.h 80 (lf *file, const insn_table *instructions, cache_entry *cache_rules);
83 /* Output a single instructions decoder */
  /src/external/gpl3/gdb.old/dist/sim/igen/
gen-icache.h 80 (lf *file, const insn_table *instructions, cache_entry *cache_rules);
83 /* Output a single instructions decoder */

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