| /src/lib/libc/arch/arm/gen/ |
| alloca.S | 40 adds r0, r0, #7 /* round up to next 8 byte alignment */
42 bics r0, r0, #7
43 sub sp, sp, r0 /* Adjust the stack pointer */
44 mov r0, sp /* r0 = base of new space */
46 lsrs r0, r0, #3
47 lsls r0, r0, #
[all...] |
| /src/common/lib/libc/arch/arm/string/ |
| ffs.S | 57 neg r1, r0
58 and r0, r0, r1
59 clz r0, r0
60 rsb r0, r0, #32
65 /* Standard trick to isolate bottom bit in r0 or 0 if r0 = 0 on entry */
66 neg r1, r0
[all...] |
| strlen_naive.S | 36 adds r3, r0, #1 /* start of src + NUL */
38 adds r2, r0, r1 /* &src[maxlen] */
41 adds ip, r0, r1 /* &src[maxlen] */
43 1: cmp r0, ip /* is this the end of string? */
46 ldrb r2, [r0] /* read a byte */
47 adds r0, r0, #1 /* advance to next byte */
49 ldrb r2, [r0], #1 /* read a byte */
53 subs r0, r0, r3 /* get difference between start and end *
[all...] |
| /src/sys/arch/powerpc/booke/ |
| spe_subr.S | 46 * r0's high half since we are about to load it.
48 evldd %r0,(8 << 4)(%r3)
49 evmra %r0,%r0
63 * The evmergelo will move the lower half of r0 to the high half of the
64 * destination register and evmergehilo will merge the high half of r0
67 evldw %r0,(30 << 2)(%r3)
68 evmergelo %r31,%r0,%r31; evmergehilo %r30,%r0,%r30
69 evldw %r0,(28 << 2)(%r3
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| nshift.s | 8 r0=0;
9 r0.h=0x8000;
11 r0 >>>= r1;
12 dbga (r0.h, 0xffff);
13 dbga (r0.l, 0xffff);
15 r0=0;
16 r0.h=0x7fff;
17 r0 >>>= r1;
18 dbga (r0.h, 0x0000);
19 dbga (r0.l, 0x0000)
[all...] |
| issue83.s | 7 R0.H = -32768;
8 R0.L = 0;
9 R0 >>= 0x1;
11 _DBG R0;
18 r0 = cc; define
19 dbga( r0.l, 0);
21 r0 = cc; define
22 dbga( r0.l, 0);
24 r0 = cc; define
25 dbga( r0.l, 0)
27 r0 = cc; define
30 r0 = cc; define
33 r0 = cc; define
46 r0 = cc; define
49 r0 = cc; define
52 r0 = cc; define
55 r0 = cc; define
58 r0 = cc; define
61 r0 = cc; define
75 r0 = cc; define
78 r0 = cc; define
81 r0 = cc; define
84 r0 = cc; define
87 r0 = cc; define
90 r0 = cc; define
[all...] |
| issue125.s | 8 R0 = -1;
11 A0.w = R0;
13 A1.w = R0;
22 // R0 = ASTAT;
23 // _DBG R0;
24 // DBGA ( R0.L , 0x0 );
25 // DBGA ( R0.H , 0x3 );
27 r0 = cc; define
28 dbga( r0.l, 0);
30 r0 = cc define
33 r0 = cc; define
36 r0 = cc; define
39 r0 = cc; define
42 r0 = cc; define
57 r0 = cc; define
60 r0 = cc; define
63 r0 = cc; define
66 r0 = cc; define
69 r0 = cc; define
72 r0 = cc; define
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| nshift.s | 8 r0=0;
9 r0.h=0x8000;
11 r0 >>>= r1;
12 dbga (r0.h, 0xffff);
13 dbga (r0.l, 0xffff);
15 r0=0;
16 r0.h=0x7fff;
17 r0 >>>= r1;
18 dbga (r0.h, 0x0000);
19 dbga (r0.l, 0x0000)
[all...] |
| issue83.s | 7 R0.H = -32768;
8 R0.L = 0;
9 R0 >>= 0x1;
11 _DBG R0;
18 r0 = cc; define
19 dbga( r0.l, 0);
21 r0 = cc; define
22 dbga( r0.l, 0);
24 r0 = cc; define
25 dbga( r0.l, 0)
27 r0 = cc; define
30 r0 = cc; define
33 r0 = cc; define
46 r0 = cc; define
49 r0 = cc; define
52 r0 = cc; define
55 r0 = cc; define
58 r0 = cc; define
61 r0 = cc; define
75 r0 = cc; define
78 r0 = cc; define
81 r0 = cc; define
84 r0 = cc; define
87 r0 = cc; define
90 r0 = cc; define
[all...] |
| issue125.s | 8 R0 = -1;
11 A0.w = R0;
13 A1.w = R0;
22 // R0 = ASTAT;
23 // _DBG R0;
24 // DBGA ( R0.L , 0x0 );
25 // DBGA ( R0.H , 0x3 );
27 r0 = cc; define
28 dbga( r0.l, 0);
30 r0 = cc define
33 r0 = cc; define
36 r0 = cc; define
39 r0 = cc; define
42 r0 = cc; define
57 r0 = cc; define
60 r0 = cc; define
63 r0 = cc; define
66 r0 = cc; define
69 r0 = cc; define
72 r0 = cc; define
[all...] |
| /src/common/lib/libc/arch/arm/gen/ |
| byte_swap_4.S | 41 rev r0, r0
43 eor r1, r0, r0, ror #16 /* d.c.b.a -> db.ca.db.ca */
45 mov r0, r0, ror #8 /* d.c.b.a -> a.d.c.b */
46 eor r0, r0, r1, lsr #8 /* a.d.c.b ^ 0.db.0.db -> a.b.c.d */
49 lsls r1, r0, #8 /* d.c.b.a -> c.b.a.0 */
50 lsrs r0, r0, #8 /* d.c.b.a -> 0.d.c.b *
[all...] |
| byte_swap_2.S | 42 rev16 r0, r0
44 and r1, r0, #0xff
45 mov r0, r0, lsr #8
46 orr r0, r0, r1, lsl #8
49 movs r1, r0
52 lsrs r0, r0, #
[all...] |
| /src/sys/external/bsd/compiler_rt/dist/lib/builtins/arm/ |
| clzdi2.S | 31 cmp r0, 0
33 clzne r0, r0
34 clzeq r0, r1
35 addeq r0, r0, 32
39 clzne r0, r1
40 clzeq r0, r0
41 addeq r0, r0, 3
[all...] |
| bswapdi2.S | 31 // r2 = rev(r0)
32 eor r2, r0, r0, ror #16
35 eor r2, r2, r0, ror #8
36 // r0 = rev(r1)
37 eor r0, r1, r1, ror #16
38 bic r0, r0, #0xff0000
39 mov r0, r0, lsr #
[all...] |
| switch16.S | 16 // case statement. On entry, R0 is the index into the table. The __switch*
19 // It then uses R0 to index into the table and get the displacement of the
20 // address to jump to. If R0 is greater than the size of the table, it jumps
35 cmp r0, ip // compare with index
36 add r0, lr, r0, lsl #1 // compute address of element in table
39 ldrshlo r0, [r0, #1] // load 16-bit element if r0 is in range
40 ldrshhs r0, [ip, #1] // load 16-bit element if r0 out of rang
[all...] |
| /src/common/lib/libc/arch/sh3/string/ |
| ffs.S | 47 mov r4,r0 ! using r0 specific instructions
48 tst #0xff,r0
52 tst r0,r0 ! ffs(0) is 0
55 shlr8 r0
56 tst #0xff,r0
60 shlr8 r0
61 tst #0xff,r0
65 shlr8 r0
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/nds32/ |
| nds32_init.inc | 15 mfsr $r0, $MSC_CFG
17 and $r2, $r0, $r1
21 la $r0, _ITB_BASE_
22 mtusr $r0, $ITB
28 mfsr $r0, $FUCOP_CTL
29 ori $r0, $r0, #0x1
30 mtsr $r0, $FUCOP_CTL
34 fmfcsr $r0
35 ori $r0,$r0,#0x100
[all...] |
| /src/external/gpl3/gcc/dist/libgcc/config/arc/ieee-754/ |
| fixsfsi.S | 35 push_s r0
37 st_s r0,[sp]
39 mov_s r0,r1
42 cmp r0,r1
53 bbit0 r0,30,.Lret0or1
54 lsr r2,r0,23
55 bmsk_s r0,r0,22
56 bset_s r0,r0,2
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/nds32/ |
| nds32_init.inc | 15 mfsr $r0, $MSC_CFG
17 and $r2, $r0, $r1
21 la $r0, _ITB_BASE_
22 mtusr $r0, $ITB
28 mfsr $r0, $FUCOP_CTL
29 ori $r0, $r0, #0x1
30 mtsr $r0, $FUCOP_CTL
34 fmfcsr $r0
35 ori $r0,$r0,#0x100
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/arc/ieee-754/ |
| fixsfsi.S | 35 push_s r0
37 st_s r0,[sp]
39 mov_s r0,r1
42 cmp r0,r1
53 bbit0 r0,30,.Lret0or1
54 lsr r2,r0,23
55 bmsk_s r0,r0,22
56 bset_s r0,r0,2
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/example-synacor/ |
| mod.s | 10 MOD r0, 8, 3
11 EQ r1, r0, 2
14 MOD r0, r0, 2
15 EQ r1, r0, 0
|
| mult.s | 10 MULT r0, 3, 2
11 EQ r1, r0, 6
14 MULT r0, r0, 8
15 EQ r1, r0, 48
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/example-synacor/ |
| mod.s | 10 MOD r0, 8, 3
11 EQ r1, r0, 2
14 MOD r0, r0, 2
15 EQ r1, r0, 0
|
| mult.s | 10 MULT r0, 3, 2
11 EQ r1, r0, 6
14 MULT r0, r0, 8
15 EQ r1, r0, 48
|
| /src/sys/arch/arm/arm/ |
| cpu_in_cksum_v4hdr.S | 36 tst r0, #4 /* 64-bit aligned? */
37 ldreqd r2, [r0], #8 /* load 1st/2nd words */
38 ldrne ip, [r0], #4 /* load 1st word */
39 ldreq ip, [r0, #8] /* load 5th word */
40 ldrned r2, [r0, #8] /* load 4th/5th words */
42 ldr ip, [r0] /* load 1st word */
43 ldr r3, [r0, #4] /* load 2nd word */
44 ldr r2, [r0, #8] /* load 3rd word */
49 ldrd r0, [r0] /* load remaining words *
[all...] |
