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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
c_dsp32shift_a0alr.s 2 // Spec Reference: dsp32shift a0 ashift, lshift, rot
21 A0 = 0;
22 A0.L = R1.L;
23 A0.H = R1.H;
24 A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */
25 R2 = A0.w; /* r5 = 0x00000000 */
29 A0.L = R2.L;
30 A0.H = R2.H
    [all...]
c_dsp32shiftim_a0alr.s 2 // Spec Reference: dsp32shift a0 ashift, lshift, rot
21 A0 = 0;
22 A0.L = R1.L;
23 A0.H = R1.H;
24 A0 = A0 << 0; /* a0 = 0x00000000 */
25 R1 = A0.w; /* r5 = 0x00000000 */
29 A0.L = R2.L;
30 A0.H = R2.H
    [all...]
c_dsp32alu_rrpm_aa.s 10 A1 = A0 = 0;
20 A0 = R0;
23 R0 = A1 + A0, R7 = A1 - A0 (NS);
24 R1 = A0 + A1, R6 = A0 - A1 (NS);
25 R2 = A1 + A0, R5 = A1 - A0 (NS);
26 R3 = A0 + A1, R4 = A0 - A1 (NS)
    [all...]
c_dsp32alu_a0_pm_a1.s 2 // Spec Reference: dsp32alu a0 += a1
10 A1 = A0 = 0;
20 A0 = R0;
23 A0 += A1;
24 A0 += A1 (W32);
25 A0 += A1;
26 A0 += A1 (W32);
27 R5 = A0.w;
30 A0 -= A1;
31 A0 -= A1 (W32)
    [all...]
s30.s 9 A1 = A0 = 0;
12 A0.w = R0;
14 A0.x = R0;
16 R5.L = SIGNBITS A0;
18 A0 = ASHIFT A0 BY R5.L;
19 _DBG A0;
21 R4 = A0.w;
22 R5 = A0.x;
27 A1 = A0 = 0
    [all...]
c_dsp32alu_awx.s 19 // A0 & A1 types
20 A0 = 0;
23 A0.L = R0.L;
24 A0.H = R0.H;
25 A0.x = R2.L;
26 R3 = A0.w;
28 R5.L = A0.x;
35 R5 = ( A0 += A1 );
36 R6.L = ( A0 += A1 );
37 R7.H = ( A0 += A1 )
    [all...]
sri.s 12 BITMUX( R6 , R7, A0) (ASR);
16 A0 = A0 >> 8;
17 R0 = A0.w;
c_dsp32alu_a_neg_a.s 20 A1 = A0 = 0;
21 A0 = R0;
23 A0 = - A0;
24 A1 = - A0;
26 A0 = - A1;
27 R1 = A0.w;
issue124.s 11 A0.w = R0;
12 A0.x = R1;
17 _DBG A0;
20 R5 = ( A0 += A1 );
22 _DBG A0;
23 R7 = A0.w; DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 );
24 R7 = A0.x; DBGA ( R7.L , 0xff80 );
c_dsp32alu_r_lh_a0pa1.s 2 // Spec Reference: dsp32alu r(lh) = ( a0 += a1)
19 A0 = R0;
21 R0 = ( A0 += A1 );
22 R1 = ( A0 += A1 );
23 R2 = ( A0 += A1 );
24 R3 = ( A0 += A1 );
25 R4 = ( A0 += A1 );
26 R5 = ( A0 += A1 );
27 R6 = ( A0 += A1 );
28 R7 = ( A0 += A1 )
    [all...]
s21.s 1 // Test A0 = ROT (A0 by imm6);
9 A0 = A1 = 0;
18 A1 = A0 = 0;
19 A0.w = R0;
20 A0 = ROT A0 BY 1;
21 R1 = A0.w;
24 R1.L = A0.x;
37 A1 = A0 = 0
    [all...]
add_sub_acc.s 1 // ACP 5.9 A0 -= A1 doesn't set flags
7 A1 = A0 = 0;
10 A0.w = R0;
12 A0.x = R0;
15 _DBG A0;
18 A0 -= A1;
19 _dbg A0;
25 A1 = A0 = 0;
28 A0.w = R0;
30 A0.x = R0
    [all...]
a25.s 7 A1 = A0 = 0;
9 A0.x = R0;
10 //A0 = 0x0100000000
19 A0.w = A1.x;
21 _DBG A0;
23 R4 = A0.w;
24 R5 = A0.x;
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
c_dsp32shift_a0alr.s 2 // Spec Reference: dsp32shift a0 ashift, lshift, rot
21 A0 = 0;
22 A0.L = R1.L;
23 A0.H = R1.H;
24 A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 */
25 R2 = A0.w; /* r5 = 0x00000000 */
29 A0.L = R2.L;
30 A0.H = R2.H
    [all...]
c_dsp32shiftim_a0alr.s 2 // Spec Reference: dsp32shift a0 ashift, lshift, rot
21 A0 = 0;
22 A0.L = R1.L;
23 A0.H = R1.H;
24 A0 = A0 << 0; /* a0 = 0x00000000 */
25 R1 = A0.w; /* r5 = 0x00000000 */
29 A0.L = R2.L;
30 A0.H = R2.H
    [all...]
c_dsp32alu_rrpm_aa.s 10 A1 = A0 = 0;
20 A0 = R0;
23 R0 = A1 + A0, R7 = A1 - A0 (NS);
24 R1 = A0 + A1, R6 = A0 - A1 (NS);
25 R2 = A1 + A0, R5 = A1 - A0 (NS);
26 R3 = A0 + A1, R4 = A0 - A1 (NS)
    [all...]
c_dsp32alu_a0_pm_a1.s 2 // Spec Reference: dsp32alu a0 += a1
10 A1 = A0 = 0;
20 A0 = R0;
23 A0 += A1;
24 A0 += A1 (W32);
25 A0 += A1;
26 A0 += A1 (W32);
27 R5 = A0.w;
30 A0 -= A1;
31 A0 -= A1 (W32)
    [all...]
s30.s 9 A1 = A0 = 0;
12 A0.w = R0;
14 A0.x = R0;
16 R5.L = SIGNBITS A0;
18 A0 = ASHIFT A0 BY R5.L;
19 _DBG A0;
21 R4 = A0.w;
22 R5 = A0.x;
27 A1 = A0 = 0
    [all...]
c_dsp32alu_awx.s 19 // A0 & A1 types
20 A0 = 0;
23 A0.L = R0.L;
24 A0.H = R0.H;
25 A0.x = R2.L;
26 R3 = A0.w;
28 R5.L = A0.x;
35 R5 = ( A0 += A1 );
36 R6.L = ( A0 += A1 );
37 R7.H = ( A0 += A1 )
    [all...]
sri.s 12 BITMUX( R6 , R7, A0) (ASR);
16 A0 = A0 >> 8;
17 R0 = A0.w;
c_dsp32alu_a_neg_a.s 20 A1 = A0 = 0;
21 A0 = R0;
23 A0 = - A0;
24 A1 = - A0;
26 A0 = - A1;
27 R1 = A0.w;
issue124.s 11 A0.w = R0;
12 A0.x = R1;
17 _DBG A0;
20 R5 = ( A0 += A1 );
22 _DBG A0;
23 R7 = A0.w; DBGA ( R7.H , 0 ); DBGA ( R7.L , 0 );
24 R7 = A0.x; DBGA ( R7.L , 0xff80 );
c_dsp32alu_r_lh_a0pa1.s 2 // Spec Reference: dsp32alu r(lh) = ( a0 += a1)
19 A0 = R0;
21 R0 = ( A0 += A1 );
22 R1 = ( A0 += A1 );
23 R2 = ( A0 += A1 );
24 R3 = ( A0 += A1 );
25 R4 = ( A0 += A1 );
26 R5 = ( A0 += A1 );
27 R6 = ( A0 += A1 );
28 R7 = ( A0 += A1 )
    [all...]
s21.s 1 // Test A0 = ROT (A0 by imm6);
9 A0 = A1 = 0;
18 A1 = A0 = 0;
19 A0.w = R0;
20 A0 = ROT A0 BY 1;
21 R1 = A0.w;
24 R1.L = A0.x;
37 A1 = A0 = 0
    [all...]
add_sub_acc.s 1 // ACP 5.9 A0 -= A1 doesn't set flags
7 A1 = A0 = 0;
10 A0.w = R0;
12 A0.x = R0;
15 _DBG A0;
18 A0 -= A1;
19 _dbg A0;
25 A1 = A0 = 0;
28 A0.w = R0;
30 A0.x = R0
    [all...]

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