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  /src/external/lgpl3/gmp/dist/mpn/arm/v7a/cora15/
mul_1.asm 1 dnl ARM mpn_mul_1 optimised for A15.
39 C Cortex-A15 2.25 this
42 C This runs well on A15 but very poorly on A9. By scheduling loads and adds
46 C This is armv5 code, optimized for the armv7a cpu A15. Its location in the
addmul_1.asm 1 dnl ARM mpn_addmul_1 optimised for A15.
39 C Cortex-A15 2 this
42 C separate from any multiply instructions. It performs well on A15, at umlal's
aors_n.asm 1 dnl ARM mpn_add_n/mpn_sub_n optimised for A15.
39 C Cortex-A15 1.27 this
44 C on A15.
com.asm 1 dnl ARM mpn_com optimised for A15.
41 C Cortex-A15 1.0
43 C This is great A15 core register code, but it is a bit large.
submul_1.asm 1 dnl ARM mpn_submul_1 optimised for A15.
39 C Cortex-A15 2.32 this
43 C A15, but not quite at the multiply bandwidth like the corresponding addmul_1
cnd_aors_n.asm 1 dnl ARM mpn_cnd_add_n/mpn_cnd_sub_n optimised for A15.
39 C Cortex-A15 1.78 this
logops_n.asm 1 dnl ARM mpn_and_n, mpn_andn_n. mpn_nand_n, etc, optimised for A15.
42 C Cortex-A15 1.27 1.64
44 C This is great A15 core register code, but it is a bit large.
  /src/external/lgpl3/gmp/dist/mpn/arm/
copyd.asm 41 C Cortex-A15 1.25
45 C and A15. But it probably slows things down for 8 <= n < a few dozen.
copyi.asm 41 C Cortex-A15 1.25
45 C and A15. But it probably slows things down for 8 <= n < a few dozen.
com.asm 39 C Cortex-A15 1.75
mode1o.asm 41 C Cortex-A15 9
aors_n.asm 41 C Cortex-A15 2.25
  /src/external/gpl3/gcc/dist/libgcc/config/c6x/
libunwind.S 61 ldw .d1t1 *+A4[15], A15
75 # Create saved register state: flags,A0-A15,B0-B15,PC = 136 bytes.
93 stw .d2t1 A15, *+B15[17]
  /src/external/gpl3/gcc.old/dist/libgcc/config/c6x/
libunwind.S 61 ldw .d1t1 *+A4[15], A15
75 # Create saved register state: flags,A0-A15,B0-B15,PC = 136 bytes.
93 stw .d2t1 A15, *+B15[17]
  /src/external/lgpl3/gmp/dist/mpn/arm/v7a/cora15/neon/
com.asm 1 dnl ARM Neon mpn_com optimised for A15.
38 C Cortex-A15 0.65
copyd.asm 1 dnl ARM Neon mpn_copyd optimised for A15.
39 C Cortex-A15 0.52
copyi.asm 1 dnl ARM Neon mpn_copyi optimised for A15.
39 C Cortex-A15 0.52
aorsorrlshC_n.asm 40 C Cortex-A15 2.25
44 C * This is ad-hoc scheduled, perhaps unnecessarily so for A15, and perhaps
rsh1aors_n.asm 41 C Cortex-A15 2.5
45 C * Try to reach 2.25 c/l on A15, to match the addlsh_1 family.
46 C * This is ad-hoc scheduled, perhaps unnecessarily so for A15, and perhaps
  /src/external/lgpl3/gmp/dist/mpn/arm/v7a/cora8/
bdiv_q_1.asm 2 dnl This is v6 code but it runs well on just the v7a Cortex-A8, A9, and A15.
43 C Cortex-A15 7 7
  /src/external/lgpl3/gmp/dist/mpn/arm/v5/
gcd_11.asm 43 C Cortex-A15 4.40 obsolete
  /src/external/lgpl3/gmp/dist/mpn/arm/v6t2/
gcd_11.asm 41 C Cortex-A15 3.2
  /src/external/lgpl3/gmp/dist/mpn/arm/neon/
lshiftc.asm 42 C Cortex-A15 1.75 1.75 Y
51 C matter for A9 or A15.
63 C either A9 or A15.
lorrshift.asm 42 C Cortex-A15 1.5 1.5 Y
51 C matter for A9 or A15.
63 C either A9 or A15.
  /src/sys/arch/hpc/conf/
platid.def 135 CPU=MIPS_VR_4111 A15 A20

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