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    Searched refs:AArch64_AM (Results 1 - 18 of 18) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ExpandImm.cpp 33 return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
82 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
97 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
223 AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
228 AArch64_AM::getShifterImm(AArch64_AM::LSL,
237 AArch64_AM::getShifterImm(AArch64_AM::LSL
    [all...]
AArch64FastISel.cpp 89 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::InvalidShiftExtend;
104 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
105 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
211 unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
215 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
243 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
401 Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
720 Addr.setExtendType(AArch64_AM::LSL)
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AArch64ISelDAGToDAG.cpp 416 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
458 static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
461 return AArch64_AM::InvalidShiftExtend;
463 return AArch64_AM::LSL;
465 return AArch64_AM::LSR;
467 return AArch64_AM::ASR;
469 return AArch64_AM::ROR;
528 AArch64_AM::ShiftExtendType ShType = getShiftTypeForNode(N);
529 if (ShType == AArch64_AM::InvalidShiftExtend
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AArch64ExpandPseudoInsts.cpp 893 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
1078 AArch64_AM::getArithExtendImm(AArch64_AM::UXTB, 0),
1083 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0),
1088 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
1093 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)
    [all...]
AArch64AsmPrinter.cpp 406 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
459 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
484 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
496 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
1327 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
AArch64InstrInfo.cpp 734 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));
739 AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
801 return AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding);
895 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
898 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5;
908 switch (AArch64_AM::getArithExtendType(Imm)) {
911 case AArch64_AM::UXTB:
912 case AArch64_AM::UXTH:
913 case AArch64_AM::UXTW
    [all...]
AArch64ConditionOptimizer.cpp 175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm());
AArch64RegisterInfo.cpp 560 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
AArch64FrameLowering.cpp 1314 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1322 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 16))
1381 .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 4))
3265 unsigned Shift = AArch64_AM::getShiftValue(MI.getOperand(3).getImm());
AArch64LoadStoreOptimizer.cpp 1124 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1779 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
1846 if (AArch64_AM::getShiftValue(MI.getOperand(3).getImm()))
AArch64ISelLowering.cpp 1559 AArch64_AM::isLogicalImmediate(Imm & Mask, Size))
1635 Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size);
7633 IsLegal = AArch64_AM::getFP64Imm(ImmInt) != -1 || Imm.isPosZero();
7635 IsLegal = AArch64_AM::getFP32Imm(ImmInt) != -1 || Imm.isPosZero();
7637 IsLegal = AArch64_AM::getFP16Imm(ImmInt) != -1 || Imm.isPosZero();
8079 if (AArch64_AM::isLogicalImmediate(CVal, 32))
8083 if (AArch64_AM::isLogicalImmediate(CVal, 64))
8095 if (AArch64_AM::isLogicalImmediate(CVal, 32))
8109 if (AArch64_AM::isLogicalImmediate(CVal, 64))
9300 if (AArch64_AM::isAdvSIMDModImmType10(Value))
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AArch64TargetTransformInfo.cpp 50 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, 64))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AddressingModes.h 25 /// AArch64_AM - AArch64 Addressing Mode Stuff
26 namespace AArch64_AM {
52 static inline const char *getShiftExtendName(AArch64_AM::ShiftExtendType ST) {
55 case AArch64_AM::LSL: return "lsl";
56 case AArch64_AM::LSR: return "lsr";
57 case AArch64_AM::ASR: return "asr";
58 case AArch64_AM::ROR: return "ror";
59 case AArch64_AM::MSL: return "msl";
60 case AArch64_AM::UXTB: return "uxtb";
61 case AArch64_AM::UXTH: return "uxth"
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AArch64InstPrinter.cpp 242 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
258 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
270 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
272 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
955 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
975 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
983 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
984 AArch64_AM::getShiftValue(Val) == 0)
986 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)
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AArch64MCCodeEmitter.cpp 265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
525 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL &&
528 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd);
555 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 342 AArch64_AM::ShiftExtendType Type;
643 AArch64_AM::ShiftExtendType getShiftExtendType() const {
804 return AArch64_AM::isLogicalImmediate(Val & ~Upper, sizeof(T) * 8);
900 AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
918 AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
939 return AArch64_AM::isAdvSIMDModImmType10(MCE->getValue());
1017 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
1032 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
1037 AArch64_AM::getFP64Imm(getFPImm().bitcastToAPInt()) != -1;
1140 AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 389 AArch64_AM::ShiftExtendType
2807 AArch64_AM::encodeLogicalImmediate(Mask, 64));
3104 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
4213 if (AArch64_AM::isLogicalImmediate(Imm, RegSize)) {
4215 TstMI.addImm(AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
5125 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
5205 static bool isSignExtendShiftType(AArch64_AM::ShiftExtendType Type) {
5207 case AArch64_AM::SXTB:
5208 case AArch64_AM::SXTH
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 1653 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1662 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1890 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))

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