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    Searched refs:ADDE (Results 1 - 25 of 25) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiAluCode.h 122 case ISD::ADDE:
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 272 ADDE,
280 /// together. The use of this opcode is preferable to adde/sube if the
TargetLowering.h 2437 case ISD::ADDE:
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativePPC_32.c 124 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
sljitNativePPC_64.c 246 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
sljitNativePPC_common.c 140 #define ADDE (HI(31) | LO(138))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelDAGToDAG.cpp 220 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
222 // The more complex case is when there is a chain of ISD::ADDE nodes like:
223 // (adde (adde (adde (addc a b) c) d) e).
227 // intermediate adde node must be expanded to write the carry bit before the
764 case ISD::ADDE: {
MipsSEISelLowering.cpp 110 setOperationAction(ISD::ADDE, MVT::i32, Legal);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 298 case ISD::ADDE: return "adde";
LegalizeIntegerTypes.cpp 159 case ISD::ADDE:
1309 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1310 // the third operand of ADDE/SUBE nodes is carry flag, which differs from
2160 case ISD::ADDE:
2580 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2582 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2595 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2692 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
SelectionDAG.cpp 3356 case ISD::ADDE: {
3359 // With ADDE and ADDCARRY, a carry bit may be added in.
3361 if (Opcode == ISD::ADDE)
TargetLowering.cpp 6395 isOperationLegalOrCustom(ISD::ADDE, VT));
6411 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
DAGCombiner.cpp 1621 case ISD::ADDE: return visitADDE(N);
2866 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2869 // fold (adde x, y, false) -> (addc x, y)
12253 // (trunc adde(X, Y, Carry)) -> (adde trunc(X), trunc(Y), Carry)
12255 // When the adde's carry is not used.
12256 if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.h 108 ADDE, // Add using carry
ARMISelLowering.cpp 1653 MAKE_CASE(ARMISD::ADDE)
4786 // using ARMISD:ADDE 0, 0, Carry
4787 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
9257 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0),
12096 // (addc (adde (mul 16bit, 16bit), lo), hi)
12171 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
12179 // ADDE <- hiAdd
12187 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE ||
12189 "Expect an ADDE or SUBE");
12193 "ADDE node has the wrong inputs")
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1558 setOperationAction(ISD::ADDE, MVT::i32, Custom);
1564 setOperationAction(ISD::ADDE, MVT::i64, Custom);
2911 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2912 case ISD::ADDE: hasChain = true; break;
3060 case ISD::ADDE:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 728 case ISD::ADDE:
1017 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
1020 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE;
R600ISelLowering.cpp 234 setOperationAction(ISD::ADDE, VT, Expand);
AMDGPUISelLowering.cpp 377 // AMDGPU uses ADDC/SUBC/ADDE/SUBE
380 setOperationAction(ISD::ADDE, VT, Legal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 107 setOperationAction(ISD::ADDE, VT, Custom);
1336 case ISD::ADDE:
2462 case ISD::ADDE:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 788 // ADDC/ADDE/SUBC/SUBE default to expand.
790 setOperationAction(ISD::ADDE, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 71 setOperationAction(ISD::ADDE, VT, Legal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 130 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 216 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
220 setOperationAction(ISD::ADDE, VT, Legal);
16579 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
16594 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 502 setOperationAction(ISD::ADDE, MVT::i32, Custom);
506 setOperationAction(ISD::ADDE, MVT::i64, Custom);
3134 case ISD::ADDE:
4498 case ISD::ADDE:

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