| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMatInt.cpp | 22 // v == 0 : ADDI
23 // v[0,12) != 0 && v[12,32) == 0 : ADDI
25 // v[0,32) != 0 : LUI+ADDI(W)
33 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
42 // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
44 // while the following ADDI instructions contribute up to 12 bits each.
48 // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
49 // fact that ADDI performs a sign extended addition, doing it like that woul
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVMergeBaseOffset.cpp | 12 // addi vreg2, vreg1, %lo(s)
13 // addi vreg3, verg2, Offset
17 // addi vreg2, vreg1, %lo(s+Offset)
43 bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
72 // addi vreg2, vreg1, %lo(s)
75 // 1) ADDI has only one use.
76 // 2) LUI has only one use; which is the ADDI.
77 // 3) Both ADDI and LUI have GlobalAddress type which indicates that these
90 if (LoADDI->getOpcode() != RISCV::ADDI ||
120 // LoADDI: addi vreg2, vreg1, %lo(s
[all...] |
| RISCVRegisterInfo.cpp | 239 if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
263 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
277 if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
292 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL)
|
| RISCVExpandPseudoInsts.cpp | 202 RISCV::ADDI);
217 SecondOpcode = RISCV::ADDI;
238 RISCV::ADDI);
|
| RISCVFrameLowering.cpp | 66 // addi s2, s2, [4|8]
71 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
114 // addi s2, s2, -[4|8]
119 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
264 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
|
| RISCVInstrInfo.cpp | 56 return MCInstBuilder(RISCV::ADDI)
125 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
813 case RISCV::ADDI:
830 case RISCV::ADDI:
1382 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N)
|
| RISCVExpandAtomicPseudoInsts.cpp | 305 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
444 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg)
|
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativePPC_64.c | 54 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm));
72 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48)));
89 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48)));
95 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48)));
105 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48)));
222 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm);
236 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)));
264 return push_inst(compiler, ADDI | D(dst) | A(src1) | (-compiler->imm & 0xffff));
|
| sljitNativePPC_32.c | 34 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm));
103 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm);
116 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)));
141 return push_inst(compiler, ADDI | D(dst) | A(src1) | (-compiler->imm & 0xffff));
|
| sljitNativeARM_64.c | 69 #define ADDI 0x91000000
577 return push_inst(compiler, ((op == SLJIT_ADD ? ADDI : SUBI) ^ inv_bits) | RD(dst) | RN(reg));
581 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (imm << 10));
590 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22));
597 FAIL_IF(push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22)));
598 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(dst) | ((imm & 0xfff) << 10));
825 return push_inst(compiler, ADDI | RD(dst) | RN(reg) | (value << 10));
827 return push_inst(compiler, ADDI | (1 << 22) | RD(dst) | RN(reg) | (value >> 2));
945 FAIL_IF(push_inst(compiler, ADDI | RD(other_r) | RN(other_r) | ((argw & 0xfff) << 10)));
947 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(other_r) | RN(other_r) | ((argw >> 12) << 10)))
[all...] |
| sljitNativePPC_common.c | 141 #define ADDI (HI(14))
628 FAIL_IF(push_inst(compiler, ADDI | D(TMP_ZERO) | A(0) | 0));
682 FAIL_IF(push_inst(compiler, ADDI | D(SLJIT_SP) | A(SLJIT_SP) | IMM(compiler->local_size)));
958 FAIL_IF(push_inst(compiler, ADDI | D(TMP_REG3) | A(TMP_REG3) | (imm & 0x3))); \
1079 FAIL_IF(push_inst(compiler, ADDI | D(TMP_REG3) | A(TMP_REG3) | IMM(diff)));
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 618 ADDI 1,arg0,arg0
625 ADDI 3,arg0,arg0
632 ADDI 7,arg0,arg0
639 ADDI 15,arg0,arg0
647 ADDI 1,arg0,arg0
662 ADDI 1,arg0,arg0
672 ADDI 3,arg0,t1
679 ADDI 1,arg0,arg0
687 ADDI 1,arg0,arg0
698 ADDI 5,arg0,t
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCMachineScheduler.cpp | 15 DisableAddiLoadHeuristic("disable-ppc-sched-addi-load",
16 cl::desc("Disable scheduling addi instruction before"
19 EnableAddiHeuristic("ppc-postra-bias-addi",
20 cl::desc("Enable scheduling addi instruction as early"
25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
155 // There are some benefits to schedule the ADDI before the load to hide the
156 // latency, as RA may create a true dependency between the load and addi.
220 // There are some benefits to schedule the ADDI as early as possible post ra
222 // And ADDI is usually used to post inc the loop indvar, which matters the
|
| PPCRegisterInfo.cpp | 107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
551 /// addi R0, SP, \#frameSize ; get the address of the previous frame
553 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
600 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
641 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
653 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer)
1342 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1420 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1450 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
|
| PPCExpandISEL.cpp | 226 // safe to fold ISEL to MR(OR) instead of ADDI.
447 TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
|
| PPCAsmPrinter.cpp | 315 // addi vs add, etc.
754 // addi r30, r30, {.LTOC,_GLOBAL_OFFSET_TABLE} - .L0$pb@l
776 MCInstBuilder(PPC::ADDI).addReg(PICR).addReg(PICR).addExpr(DeltaLo));
1178 // Into: %rd = ADDI %rs, sym@got@tlsgd
1187 MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI)
1229 // Into: %rd = ADDI %rs, sym@got@tlsld
1238 MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI)
1294 // Into: %rd = ADDI %rs, sym@dtprel@l
1302 MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI)
1651 // addi r2,r2,(.TOC.-.Lfunc_gepNN)@
[all...] |
| PPCFastISel.cpp | 402 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
1312 Opc = PPC::ADDI;
1329 Opc = PPC::ADDI;
2413 // Override for ADDI and ADDI8 to set the correct register class
2422 // register classes, as any such result could be used in ADDI, etc.,
2428 if (MachineInstOpcode == PPC::ADDI)
|
| /src/external/gpl3/gdb.old/dist/gdb/ |
| nds32-tdep.c | 631 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
633 /* addi $sp, $sp, imm15s */
645 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
647 /* addi $fp, $sp, imm15s */
708 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
710 /* addi $ta, $ta, imm15s */
1072 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1074 /* addi $sp, $sp, imm15s */
1076 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1078 /* addi $sp, $fp, imm15s *
[all...] |
| riscv-tdep.c | 1559 ADDI,
1890 decode_i_type_insn (ADDI, ival);
1998 decode_ci_type_insn (ADDI, ival);
2010 m_opcode = ADDI;
2016 m_opcode = ADDI;
2118 return ((insn.opcode () == riscv_insn::ADDI
2347 /* Handle: addi sp, sp, -i
2370 else if (insn.opcode () == riscv_insn::ADDI
2374 /* Handle: addi s0, sp, size */
2394 else if ((insn.opcode () == riscv_insn::ADDI
[all...] |
| /src/external/gpl3/gdb/dist/gdb/ |
| nds32-tdep.c | 631 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
633 /* addi $sp, $sp, imm15s */
645 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
647 /* addi $fp, $sp, imm15s */
708 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
710 /* addi $ta, $ta, imm15s */
1072 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1074 /* addi $sp, $sp, imm15s */
1076 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1078 /* addi $sp, $fp, imm15s *
[all...] |
| riscv-tdep.c | 1576 ADDI,
1907 decode_i_type_insn (ADDI, ival);
2015 decode_ci_type_insn (ADDI, ival);
2027 m_opcode = ADDI;
2033 m_opcode = ADDI;
2135 return ((insn.opcode () == riscv_insn::ADDI
2364 /* Handle: addi sp, sp, -i
2387 else if (insn.opcode () == riscv_insn::ADDI
2391 /* Handle: addi s0, sp, size */
2411 else if ((insn.opcode () == riscv_insn::ADDI
[all...] |
| /src/external/gpl3/gcc/dist/libgcc/config/microblaze/ |
| moddi3.S | 92 ADDI r30,r30,1
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/microblaze/ |
| moddi3.S | 92 ADDI r30,r30,1
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| RISCVAsmParser.cpp | 99 // Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that
2265 // ADDI rdest, rdest, %pcrel_lo(TmpLabel)
2269 RISCV::ADDI, IDLoc, Out);
2279 // ADDI rdest, rdest, %pcrel_lo(TmpLabel)
2291 SecondOpcode = RISCV::ADDI;
2319 // ADDI rdest, rdest, %pcrel_lo(TmpLabel)
2323 RISCV::ADDI, IDLoc, Out);
2544 // Just convert to an addi. This allows compatibility with gas.
2545 emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
|
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| riscv.h | 245 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
600 /* Instruction is a simple alias (e.g. "mv" for "addi"). */
|
