| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
59 // A single ADDiu will do if RemSize <= 16.
61 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
74 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
83 // Replace a ADDiu & SLL pair with a LUi.
85 // ADDiu 0x0111
90 // Check if the first two instructions are ADDiu and SLL and the shift amount
92 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
96 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit.
134 ADDiu = Mips::ADDiu
[all...] |
| MipsAnalyzeImmediate.h | 27 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is
37 /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to
52 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
60 unsigned ADDiu, ORi, SLL, LUi;
|
| MipsInstructionSelector.cpp | 160 // ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
692 MachineInstr *ADDiu =
693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
697 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
698 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
711 MachineInstr *ADDiu =
712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
716 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO)
[all...] |
| MipsMachineFunction.cpp | 100 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
114 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
130 // 1. addiu $2, $2, %lo(_gp_disp)
141 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
|
| MipsBranchExpansion.cpp | 436 // addiu $sp, $sp, -8
440 // addiu $at, $at, %lo($tgt - $baltgt)
445 // addiu $sp, $sp, 8
451 // addiu $sp, $sp, -8
454 // addiu $at, $at, %lo($tgt - $baltgt)
459 // addiu $sp, $sp, 8
465 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
473 // LUi and ADDiu instructions create 32-bit offset of the target basic
482 // we replace LUi and ADDiu with pseudo instructions
485 // instructions to LUi and ADDiu in the MC layer, we will creat
[all...] |
| MipsMCInstLower.cpp | 306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
|
| MicroMipsSizeReduction.cpp | 180 // Attempts to reduce ADDIU into ADDIUSP instruction,
184 // Attempts to reduce ADDIU into ADDIUR1SP instruction,
214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
|
| MipsSEISelDAGToDAG.cpp | 87 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
88 if ((MI.getOpcode() == Mips::ADDiu) &&
146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
340 // addiu $2, $2, %lo($CPI1_0)
813 // instructions (ADDiu, ORI and SLL) in that it does not have a register
1113 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
|
| MipsFastISel.cpp | 368 unsigned Opc = Mips::ADDiu;
427 emitInst(Mips::ADDiu, TempReg)
742 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
743 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
|
| MipsSEFrameLowering.cpp | 418 unsigned ADDiu = ABI.GetPtrAddiuOp();
539 // addiu $Reg, $zero, -MaxAlignment
546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign);
|
| MipsSEInstrInfo.cpp | 594 unsigned ADDiu = ABI.GetPtrAddiuOp();
601 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
638 // instructions (ADDiu, ORI and SLL) in that it does not have a register
|
| MipsAsmPrinter.cpp | 310 // addiu $sp, $sp, -48
1149 // ADDIU T9, T9, 52
1156 // ADDIU SP, SP, -8
1167 // ADDIU SP, SP, 8
1201 // ADDIU T0, T0, %lo(function_id)
1230 MCInstBuilder(Mips::ADDiu)
|
| MipsInstrInfo.cpp | 856 // Ex. $a2 = ADDiu $zero, 10
884 case Mips::ADDiu:
|
| MipsSEISelLowering.cpp | 3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3137 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3143 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
|
| MipsISelLowering.cpp | 735 // addiu $reg2, $reg1, y-1
742 // addiu $reg2, $reg1, y-1
1767 // addiu masklsb2,$0,-4 # 0xfffffffc
1951 // addiu masklsb2,$0,-4 # 0xfffffffc
1964 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsABIInfo.cpp | 102 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
|
| MipsTargetStreamer.cpp | 1156 // addiu $gp, $gp, %lo(__gnu_local_gp)
1176 TmpInst.setOpcode(Mips::ADDiu);
1258 // addiu $gp, $gp, %lo(__gnu_local_gp)
1259 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1275 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1276 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 2552 case Mips::ADDiu: case Mips::ADDiu_MM:
2744 // traditional assembler behaviour. N32 would normally use addiu for both
2751 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2983 // >addiu $tmp, $tmp, offset
2984 // >addiu $rd, $tmp, $rs
2985 // The addiu's marked with a '>' may be omitted if they are redundant. If
3001 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3041 // >addiu $tmp, $tmp, offset
3042 // >addiu $rd, $tmp, $rs
3044 // addiu $tmp, $tmp, %lo(symbol+offset)($gp
[all...] |
