1 /* $NetBSD: dbcool.c,v 1.69 2026/07/07 12:42:58 jdc Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Goyette 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * a driver for the dbCool(tm) family of environmental controllers 34 * 35 * Data sheets for the various supported chips are available at 36 * 37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF 38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF 39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF 40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF 41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF 42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF 43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF 44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF 45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF 46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF 47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf 48 * 49 * (URLs are correct as of October 5, 2008) 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.69 2026/07/07 12:42:58 jdc Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/device.h> 59 #include <sys/sysctl.h> 60 #include <sys/module.h> 61 62 #include <dev/i2c/dbcool_var.h> 63 #include <dev/i2c/dbcool_reg.h> 64 65 /* Config interface */ 66 static int dbcool_match(device_t, cfdata_t, void *); 67 static void dbcool_attach(device_t, device_t, void *); 68 static int dbcool_detach(device_t, int); 69 70 /* Device attributes */ 71 static int dbcool_supply_voltage(struct dbcool_softc *); 72 static bool dbcool_islocked(struct dbcool_softc *); 73 74 /* Sensor read functions */ 75 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *); 76 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t); 77 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool); 78 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool); 79 80 /* Sensor get/set limit functions */ 81 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *, 82 sysmon_envsys_lim_t *, uint32_t *); 83 static void dbcool_get_temp_limits(struct dbcool_softc *, int, 84 sysmon_envsys_lim_t *, uint32_t *); 85 static void dbcool_get_volt_limits(struct dbcool_softc *, int, 86 sysmon_envsys_lim_t *, uint32_t *); 87 static void dbcool_get_fan_limits(struct dbcool_softc *, int, 88 sysmon_envsys_lim_t *, uint32_t *); 89 90 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *, 91 sysmon_envsys_lim_t *, uint32_t *); 92 static void dbcool_set_temp_limits(struct dbcool_softc *, int, 93 sysmon_envsys_lim_t *, uint32_t *); 94 static void dbcool_set_volt_limits(struct dbcool_softc *, int, 95 sysmon_envsys_lim_t *, uint32_t *); 96 static void dbcool_set_fan_limits(struct dbcool_softc *, int, 97 sysmon_envsys_lim_t *, uint32_t *); 98 99 /* SYSCTL Helpers */ 100 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup); 101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO); 102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO); 103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO); 104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO); 105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO); 106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO); 107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO); 108 109 /* Set-up subroutines */ 110 static void dbcool_setup_controllers(struct dbcool_softc *); 111 static int dbcool_setup_sensors(struct dbcool_softc *); 112 static int dbcool_attach_sensor(struct dbcool_softc *, int); 113 static int dbcool_attach_temp_control(struct dbcool_softc *, int, 114 struct chip_id *); 115 116 #ifdef DBCOOL_DEBUG 117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO); 118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO); 119 #endif /* DBCOOL_DEBUG */ 120 121 /* 122 * Descriptions for SYSCTL entries 123 */ 124 struct dbc_sysctl_info { 125 const char *name; 126 const char *desc; 127 bool lockable; 128 int (*helper)(SYSCTLFN_PROTO); 129 }; 130 131 static struct dbc_sysctl_info dbc_sysctl_table[] = { 132 /* 133 * The first several entries must remain in the same order as the 134 * corresponding entries in enum dbc_pwm_params 135 */ 136 { "behavior", "operating behavior and temp selector", 137 true, sysctl_dbcool_behavior }, 138 { "min_duty", "minimum fan controller PWM duty cycle", 139 true, sysctl_dbcool_duty }, 140 { "max_duty", "maximum fan controller PWM duty cycle", 141 true, sysctl_dbcool_duty }, 142 { "cur_duty", "current fan controller PWM duty cycle", 143 false, sysctl_dbcool_duty }, 144 145 /* 146 * The rest of these should be in the order in which they 147 * are to be stored in the sysctl tree; the table index is 148 * used as the high-order bits of the sysctl_num to maintain 149 * the sequence. 150 * 151 * If you rearrange the order of these items, be sure to 152 * update the sysctl_index in the XXX_sensor_table[] for 153 * the various chips! 154 */ 155 { "Trange", "temp slope/range to reach 100% duty cycle", 156 true, sysctl_dbcool_slope }, 157 { "Tmin", "temp at which to start fan controller", 158 true, sysctl_dbcool_temp }, 159 { "Ttherm", "temp at which THERM is asserted", 160 true, sysctl_dbcool_temp }, 161 { "Thyst", "temp hysteresis for stopping fan controller", 162 true, sysctl_dbcool_thyst }, 163 { "Tmin", "temp at which to start fan controller", 164 true, sysctl_adm1030_temp }, 165 { "Trange", "temp slope/range to reach 100% duty cycle", 166 true, sysctl_adm1030_trange }, 167 }; 168 169 static const char *dbc_sensor_names[] = { 170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1", 171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5", 172 "V5", "V12", "Vtt", "Imon", "VID" 173 }; 174 175 /* 176 * Following table derived from product data-sheets 177 */ 178 static int64_t nominal_voltages[] = { 179 -1, /* Vcc can be either 3.3 or 5.0V 180 at 3/4 scale */ 181 2249939, /* Vccp 2.25V 3/4 scale */ 182 2497436, /* 2.5VIN 2.5V 3/4 scale */ 183 5002466, /* 5VIN 5V 3/4 scale */ 184 12000000, /* 12VIN 12V 3/4 scale */ 185 1690809, /* Vtt, Imon 2.25V full scale */ 186 1689600, /* AIN1, AIN2 2.25V full scale */ 187 0 188 }; 189 190 /* 191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx, 192 * nom-voltage-index 193 */ 194 struct dbcool_sensor ADT7490_sensor_table[] = { 195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 196 DBCOOL_LOCAL_HIGHLIM, 197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 199 DBCOOL_REMOTE1_HIGHLIM, 200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 202 DBCOOL_REMOTE2_HIGHLIM, 203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 204 { DBC_VOLT, { DBCOOL_VCCP, 205 DBCOOL_VCCP_HIGHLIM, 206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 207 { DBC_VOLT, { DBCOOL_VCC, 208 DBCOOL_VCC_HIGHLIM, 209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 210 { DBC_VOLT, { DBCOOL_25VIN, 211 DBCOOL_25VIN_HIGHLIM, 212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 213 { DBC_VOLT, { DBCOOL_5VIN, 214 DBCOOL_5VIN_HIGHLIM, 215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 216 { DBC_VOLT, { DBCOOL_12VIN, 217 DBCOOL_12VIN_HIGHLIM, 218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 219 { DBC_VOLT, { DBCOOL_VTT, 220 DBCOOL_VTT_HIGHLIM, 221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 }, 222 { DBC_VOLT, { DBCOOL_IMON, 223 DBCOOL_IMON_HIGHLIM, 224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 }, 225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 226 DBCOOL_NO_REG, 227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 229 DBCOOL_NO_REG, 230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 232 DBCOOL_NO_REG, 233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 235 DBCOOL_NO_REG, 236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 237 { DBC_VID, { DBCOOL_VID_REG, 238 DBCOOL_NO_REG, 239 DBCOOL_NO_REG }, 16, 0, 0 }, 240 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 241 DBCOOL_NO_REG, 242 DBCOOL_NO_REG }, 0, 5, 0 }, 243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 244 DBCOOL_NO_REG, 245 DBCOOL_NO_REG }, 0, 6, 0 }, 246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 247 DBCOOL_NO_REG, 248 DBCOOL_NO_REG }, 0, 7, 0 }, 249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 250 DBCOOL_NO_REG, 251 DBCOOL_NO_REG }, 1, 5, 0 }, 252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 253 DBCOOL_NO_REG, 254 DBCOOL_NO_REG }, 1, 6, 0 }, 255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 256 DBCOOL_NO_REG, 257 DBCOOL_NO_REG }, 1, 7, 0 }, 258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 259 DBCOOL_NO_REG, 260 DBCOOL_NO_REG }, 2, 5, 0 }, 261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 262 DBCOOL_NO_REG, 263 DBCOOL_NO_REG }, 2, 6, 0 }, 264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 265 DBCOOL_NO_REG, 266 DBCOOL_NO_REG }, 2, 7, 0 }, 267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 268 }; 269 270 struct dbcool_sensor ADT7476_sensor_table[] = { 271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 272 DBCOOL_LOCAL_HIGHLIM, 273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 275 DBCOOL_REMOTE1_HIGHLIM, 276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 278 DBCOOL_REMOTE2_HIGHLIM, 279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 280 { DBC_VOLT, { DBCOOL_VCCP, 281 DBCOOL_VCCP_HIGHLIM, 282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 283 { DBC_VOLT, { DBCOOL_VCC, 284 DBCOOL_VCC_HIGHLIM, 285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 286 { DBC_VOLT, { DBCOOL_25VIN, 287 DBCOOL_25VIN_HIGHLIM, 288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 289 { DBC_VOLT, { DBCOOL_5VIN, 290 DBCOOL_5VIN_HIGHLIM, 291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 292 { DBC_VOLT, { DBCOOL_12VIN, 293 DBCOOL_12VIN_HIGHLIM, 294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 296 DBCOOL_NO_REG, 297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 299 DBCOOL_NO_REG, 300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 302 DBCOOL_NO_REG, 303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 305 DBCOOL_NO_REG, 306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 307 { DBC_VID, { DBCOOL_VID_REG, 308 DBCOOL_NO_REG, 309 DBCOOL_NO_REG }, 16, 0, 0 }, 310 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 311 DBCOOL_NO_REG, 312 DBCOOL_NO_REG }, 0, 5, 0 }, 313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 314 DBCOOL_NO_REG, 315 DBCOOL_NO_REG }, 0, 6, 0 }, 316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 317 DBCOOL_NO_REG, 318 DBCOOL_NO_REG }, 0, 7, 0 }, 319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 320 DBCOOL_NO_REG, 321 DBCOOL_NO_REG }, 1, 5, 0 }, 322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 323 DBCOOL_NO_REG, 324 DBCOOL_NO_REG }, 1, 6, 0 }, 325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 326 DBCOOL_NO_REG, 327 DBCOOL_NO_REG }, 1, 7, 0 }, 328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 329 DBCOOL_NO_REG, 330 DBCOOL_NO_REG }, 2, 5, 0 }, 331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 332 DBCOOL_NO_REG, 333 DBCOOL_NO_REG }, 2, 6, 0 }, 334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 335 DBCOOL_NO_REG, 336 DBCOOL_NO_REG }, 2, 7, 0 }, 337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 338 }; 339 340 struct dbcool_sensor ADT7475_sensor_table[] = { 341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 342 DBCOOL_LOCAL_HIGHLIM, 343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 345 DBCOOL_REMOTE1_HIGHLIM, 346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 348 DBCOOL_REMOTE2_HIGHLIM, 349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 350 { DBC_VOLT, { DBCOOL_VCCP, 351 DBCOOL_VCCP_HIGHLIM, 352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 353 { DBC_VOLT, { DBCOOL_VCC, 354 DBCOOL_VCC_HIGHLIM, 355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 357 DBCOOL_NO_REG, 358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 360 DBCOOL_NO_REG, 361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 363 DBCOOL_NO_REG, 364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 366 DBCOOL_NO_REG, 367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 368 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 369 DBCOOL_NO_REG, 370 DBCOOL_NO_REG }, 0, 5, 0 }, 371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 372 DBCOOL_NO_REG, 373 DBCOOL_NO_REG }, 0, 6, 0 }, 374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 375 DBCOOL_NO_REG, 376 DBCOOL_NO_REG }, 0, 7, 0 }, 377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 378 DBCOOL_NO_REG, 379 DBCOOL_NO_REG }, 1, 5, 0 }, 380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 381 DBCOOL_NO_REG, 382 DBCOOL_NO_REG }, 1, 6, 0 }, 383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 384 DBCOOL_NO_REG, 385 DBCOOL_NO_REG }, 1, 7, 0 }, 386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 387 DBCOOL_NO_REG, 388 DBCOOL_NO_REG }, 2, 5, 0 }, 389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 390 DBCOOL_NO_REG, 391 DBCOOL_NO_REG }, 2, 6, 0 }, 392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 393 DBCOOL_NO_REG, 394 DBCOOL_NO_REG }, 2, 7, 0 }, 395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 396 }; 397 398 /* 399 * The registers of dbcool_power_control must be in the same order as 400 * in enum dbc_pwm_params 401 */ 402 struct dbcool_power_control ADT7475_power_table[] = { 403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY, 404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY }, 405 "fan_control_1" }, 406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY, 407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY }, 408 "fan_control_2" }, 409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY, 410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY }, 411 "fan_control_3" }, 412 { { 0, 0, 0, 0 }, NULL } 413 }; 414 415 struct dbcool_sensor ADT7466_sensor_table[] = { 416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB, 417 DBCOOL_ADT7466_LCL_TEMP_HILIM, 418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 }, 419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB, 420 DBCOOL_ADT7466_REM_TEMP_HILIM, 421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 }, 422 { DBC_VOLT, { DBCOOL_ADT7466_VCC, 423 DBCOOL_ADT7466_VCC_HILIM, 424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 }, 425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1, 426 DBCOOL_ADT7466_AIN1_HILIM, 427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 }, 428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2, 429 DBCOOL_ADT7466_AIN2_HILIM, 430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 }, 431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB, 432 DBCOOL_NO_REG, 433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 }, 434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB, 435 DBCOOL_NO_REG, 436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 }, 437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 438 }; 439 440 struct dbcool_sensor ADM1027_sensor_table[] = { 441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 442 DBCOOL_LOCAL_HIGHLIM, 443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 445 DBCOOL_REMOTE1_HIGHLIM, 446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 448 DBCOOL_REMOTE2_HIGHLIM, 449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 450 { DBC_VOLT, { DBCOOL_VCCP, 451 DBCOOL_VCCP_HIGHLIM, 452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 453 { DBC_VOLT, { DBCOOL_VCC, 454 DBCOOL_VCC_HIGHLIM, 455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 456 { DBC_VOLT, { DBCOOL_25VIN, 457 DBCOOL_25VIN_HIGHLIM, 458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 459 { DBC_VOLT, { DBCOOL_5VIN, 460 DBCOOL_5VIN_HIGHLIM, 461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 462 { DBC_VOLT, { DBCOOL_12VIN, 463 DBCOOL_12VIN_HIGHLIM, 464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 466 DBCOOL_NO_REG, 467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 469 DBCOOL_NO_REG, 470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 472 DBCOOL_NO_REG, 473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 475 DBCOOL_NO_REG, 476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 477 { DBC_VID, { DBCOOL_VID_REG, 478 DBCOOL_NO_REG, 479 DBCOOL_NO_REG }, 16, 0, 0 }, 480 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 481 DBCOOL_NO_REG, 482 DBCOOL_NO_REG }, 0, 5, 0 }, 483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 484 DBCOOL_NO_REG, 485 DBCOOL_NO_REG }, 0, 6, 0 }, 486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80, 487 DBCOOL_NO_REG, 488 DBCOOL_NO_REG }, 0, 7, 0 }, 489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 490 DBCOOL_NO_REG, 491 DBCOOL_NO_REG }, 1, 5, 0 }, 492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 493 DBCOOL_NO_REG, 494 DBCOOL_NO_REG }, 1, 6, 0 }, 495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST, 496 DBCOOL_NO_REG, 497 DBCOOL_NO_REG }, 1, 7, 0 }, 498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 499 DBCOOL_NO_REG, 500 DBCOOL_NO_REG }, 2, 5, 0 }, 501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 502 DBCOOL_NO_REG, 503 DBCOOL_NO_REG }, 2, 6, 0 }, 504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST, 505 DBCOOL_NO_REG, 506 DBCOOL_NO_REG }, 2, 7, 0 }, 507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 508 }; 509 510 struct dbcool_sensor ADM1030_sensor_table[] = { 511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 512 DBCOOL_ADM1030_L_HI_LIM, 513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 515 DBCOOL_ADM1030_R_HI_LIM, 516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 518 DBCOOL_NO_REG, 519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 521 DBCOOL_NO_REG, 522 DBCOOL_NO_REG }, 0, 8, 0 }, 523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 524 DBCOOL_NO_REG, 525 DBCOOL_NO_REG }, 0, 9, 0 }, 526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 527 DBCOOL_NO_REG, 528 DBCOOL_NO_REG }, 0, 6, 0 }, 529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 530 DBCOOL_NO_REG, 531 DBCOOL_NO_REG }, 1, 8, 0 }, 532 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 533 DBCOOL_NO_REG, 534 DBCOOL_NO_REG }, 1, 9, 0 }, 535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 536 DBCOOL_NO_REG, 537 DBCOOL_NO_REG }, 1, 6, 0 }, 538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 539 }; 540 541 struct dbcool_power_control ADM1030_power_table[] = { 542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 543 DBCOOL_ADM1030_FAN_SPEED_CFG }, 544 "fan_control_1" }, 545 { { 0, 0, 0, 0 }, NULL } 546 }; 547 548 struct dbcool_sensor ADM1031_sensor_table[] = { 549 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP, 550 DBCOOL_ADM1030_L_HI_LIM, 551 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 }, 552 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP, 553 DBCOOL_ADM1030_R_HI_LIM, 554 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 }, 555 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP, 556 DBCOOL_ADM1031_R2_HI_LIM, 557 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 }, 558 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH, 559 DBCOOL_NO_REG, 560 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 }, 561 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH, 562 DBCOOL_NO_REG, 563 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 }, 564 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN, 565 DBCOOL_NO_REG, 566 DBCOOL_NO_REG }, 0, 8, 0 }, 567 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 568 DBCOOL_NO_REG, 569 DBCOOL_NO_REG }, 0, 9, 0 }, 570 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH, 571 DBCOOL_NO_REG, 572 DBCOOL_NO_REG }, 0, 6, 0 }, 573 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN, 574 DBCOOL_NO_REG, 575 DBCOOL_NO_REG }, 1, 8, 0 }, 576 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 577 DBCOOL_NO_REG, 578 DBCOOL_NO_REG }, 1, 9, 0 }, 579 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH, 580 DBCOOL_NO_REG, 581 DBCOOL_NO_REG }, 1, 6, 0 }, 582 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN, 583 DBCOOL_NO_REG, 584 DBCOOL_NO_REG }, 2, 8, 0 }, 585 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 586 DBCOOL_NO_REG, 587 DBCOOL_NO_REG }, 2, 9, 0 }, 588 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH, 589 DBCOOL_NO_REG, 590 DBCOOL_NO_REG }, 2, 6, 0 }, 591 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 } 592 }; 593 594 struct dbcool_power_control ADM1031_power_table[] = { 595 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 596 DBCOOL_ADM1030_FAN_SPEED_CFG }, 597 "fan_control_1" }, 598 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG, 599 DBCOOL_ADM1030_FAN_SPEED_CFG }, 600 "fan_control_2" }, 601 { { 0, 0, 0, 0 }, NULL } 602 }; 603 604 struct dbcool_sensor EMC6D103S_sensor_table[] = { 605 { DBC_TEMP, { DBCOOL_LOCAL_TEMP, 606 DBCOOL_LOCAL_HIGHLIM, 607 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 }, 608 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP, 609 DBCOOL_REMOTE1_HIGHLIM, 610 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 }, 611 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP, 612 DBCOOL_REMOTE2_HIGHLIM, 613 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 }, 614 { DBC_VOLT, { DBCOOL_VCCP, 615 DBCOOL_VCCP_HIGHLIM, 616 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 }, 617 { DBC_VOLT, { DBCOOL_VCC, 618 DBCOOL_VCC_HIGHLIM, 619 DBCOOL_VCC_LOWLIM }, 4, 0, 0 }, 620 { DBC_VOLT, { DBCOOL_25VIN, 621 DBCOOL_25VIN_HIGHLIM, 622 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 }, 623 { DBC_VOLT, { DBCOOL_5VIN, 624 DBCOOL_5VIN_HIGHLIM, 625 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 }, 626 { DBC_VOLT, { DBCOOL_12VIN, 627 DBCOOL_12VIN_HIGHLIM, 628 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 }, 629 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB, 630 DBCOOL_NO_REG, 631 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 }, 632 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB, 633 DBCOOL_NO_REG, 634 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 }, 635 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB, 636 DBCOOL_NO_REG, 637 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 }, 638 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB, 639 DBCOOL_NO_REG, 640 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 }, 641 { DBC_VID, { DBCOOL_VID_REG, 642 DBCOOL_NO_REG, 643 DBCOOL_NO_REG }, 16, 0, 0 }, 644 { DBC_CTL, { DBCOOL_LOCAL_TMIN, 645 DBCOOL_NO_REG, 646 DBCOOL_NO_REG }, 0, 5, 0 }, 647 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH, 648 DBCOOL_NO_REG, 649 DBCOOL_NO_REG }, 0, 6, 0 }, 650 { DBC_CTL, { DBCOOL_REMOTE1_TMIN, 651 DBCOOL_NO_REG, 652 DBCOOL_NO_REG }, 1, 5, 0 }, 653 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH, 654 DBCOOL_NO_REG, 655 DBCOOL_NO_REG }, 1, 6, 0 }, 656 { DBC_CTL, { DBCOOL_REMOTE2_TMIN, 657 DBCOOL_NO_REG, 658 DBCOOL_NO_REG }, 2, 5, 0 }, 659 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH, 660 DBCOOL_NO_REG, 661 DBCOOL_NO_REG }, 2, 6, 0 }, 662 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 } 663 }; 664 665 struct chip_id chip_table[] = { 666 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID, 667 ADT7490_sensor_table, ADT7475_power_table, 668 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI, 669 90000 * 60, "ADT7490" }, 670 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff, 671 ADT7476_sensor_table, ADT7475_power_table, 672 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY, 673 90000 * 60, "ADT7476" }, 674 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff, 675 ADT7475_sensor_table, ADT7475_power_table, 676 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 677 90000 * 60, "ADT7475" }, 678 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1, 679 ADT7475_sensor_table, ADT7475_power_table, 680 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 681 90000 * 60, "ADT7460/ADT7463" }, 682 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2, 683 ADT7475_sensor_table, ADT7475_power_table, 684 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN, 685 90000 * 60, "ADT7463-1" }, 686 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff, 687 ADT7476_sensor_table, ADT7475_power_table, 688 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY | 689 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 690 90000 * 60, "ADT7467/ADT7468" }, 691 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff, 692 ADT7466_sensor_table, NULL, 693 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN, 694 82000 * 60, "ADT7466" }, 695 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1, 696 ADM1027_sensor_table, ADT7475_power_table, 697 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN, 698 90000 * 60, "ADT7463" }, 699 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2, 700 ADM1027_sensor_table, ADT7475_power_table, 701 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN | 702 DBCFLAG_HAS_VID_SEL, 703 90000 * 60, "ADT7463" }, 704 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID, 705 ADM1027_sensor_table, ADT7475_power_table, 706 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER, 707 90000 * 60, "ADM1027" }, 708 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff, 709 ADM1030_sensor_table, ADM1030_power_table, 710 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 711 11250 * 60, "ADM1030" }, 712 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff, 713 ADM1031_sensor_table, ADM1030_power_table, 714 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE, 715 11250 * 60, "ADM1031" }, 716 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID, 717 EMC6D103S_sensor_table, ADT7475_power_table, 718 DBCFLAG_4BIT_VER, 719 90000 * 60, "EMC6D103S" }, 720 { 0, 0, 0, NULL, NULL, 0, 0, NULL } 721 }; 722 723 static const char *behavior[] = { 724 "remote1", "local", "remote2", "full-speed", 725 "disabled", "local+remote2","all-temps", "manual" 726 }; 727 728 static char dbcool_cur_behav[16]; 729 730 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc), 731 dbcool_match, dbcool_attach, dbcool_detach, NULL); 732 733 static const struct device_compatible_entry compat_data[] = { 734 { .compat = "i2c-adm1031" }, 735 { .compat = "i2c-adt7475" }, 736 { .compat = "adt7467" }, 737 { .compat = "adt7460" }, 738 { .compat = "adm1030" }, 739 DEVICE_COMPAT_EOL 740 }; 741 742 int 743 dbcool_match(device_t parent, cfdata_t cf, void *aux) 744 { 745 struct i2c_attach_args *ia = aux; 746 struct dbcool_chipset dc; 747 dc.dc_tag = ia->ia_tag; 748 dc.dc_addr = ia->ia_addr; 749 dc.dc_chip = NULL; 750 dc.dc_readreg = dbcool_readreg; 751 dc.dc_writereg = dbcool_writereg; 752 int match_result; 753 754 if (iic_use_direct_match(ia, cf, compat_data, &match_result)) 755 return match_result; 756 757 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR) 758 return 0; 759 if (dbcool_chip_ident(&dc) >= 0) 760 return I2C_MATCH_ADDRESS_AND_PROBE; 761 762 return 0; 763 } 764 765 void 766 dbcool_attach(device_t parent, device_t self, void *aux) 767 { 768 struct dbcool_softc *sc = device_private(self); 769 struct i2c_attach_args *args = aux; 770 uint8_t ver; 771 772 sc->sc_dc.dc_addr = args->ia_addr; 773 sc->sc_dc.dc_tag = args->ia_tag; 774 sc->sc_dc.dc_chip = NULL; 775 sc->sc_dc.dc_readreg = dbcool_readreg; 776 sc->sc_dc.dc_writereg = dbcool_writereg; 777 sc->sc_dev = self; 778 779 if (dbcool_chip_ident(&sc->sc_dc) < 0 || sc->sc_dc.dc_chip == NULL) 780 panic("could not identify chip at addr %d", args->ia_addr); 781 782 aprint_naive("\n"); 783 aprint_normal("\n"); 784 785 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG); 786 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER) 787 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID) 788 { 789 aprint_normal_dev(self, "SMSC %s Controller " 790 "(rev 0x%02x, stepping 0x%02x)\n", 791 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 792 } else { 793 aprint_normal_dev(self, "%s dBCool(tm) Controller " 794 "(rev 0x%02x, stepping 0x%02x)\n", 795 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f); 796 } 797 else 798 aprint_normal_dev(self, "%s dBCool(tm) Controller " 799 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver); 800 801 sc->sc_sysctl_log = NULL; 802 803 #ifdef _MODULE 804 sysctl_dbcoolsetup(&sc->sc_sysctl_log); 805 #endif 806 807 dbcool_setup(self); 808 809 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume)) 810 aprint_error_dev(self, "couldn't establish power handler\n"); 811 } 812 813 static int 814 dbcool_detach(device_t self, int flags) 815 { 816 struct dbcool_softc *sc = device_private(self); 817 818 pmf_device_deregister(self); 819 820 if (sc->sc_sme != NULL) 821 sysmon_envsys_unregister(sc->sc_sme); 822 823 sysctl_teardown(&sc->sc_sysctl_log); 824 825 return 0; 826 } 827 828 /* 829 * On suspend, we save the state of the SHDN bit, then set it 830 * On resume, we restore the previous state of the SHDN bit (which 831 * we saved in sc_suspend) 832 */ 833 static bool 834 dbcool_do_pmf(device_t dev, const pmf_qual_t *qual, bool suspend) 835 { 836 struct dbcool_softc *sc = device_private(dev); 837 uint8_t reg, bit, cfg; 838 839 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0) 840 return true; 841 842 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 843 reg = DBCOOL_ADT7466_CONFIG2; 844 bit = DBCOOL_ADT7466_CFG2_SHDN; 845 } else { 846 reg = DBCOOL_CONFIG2_REG; 847 bit = DBCOOL_CFG2_SHDN; 848 } 849 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 850 if (suspend) { 851 sc->sc_suspend = (cfg & bit) != 0; 852 cfg |= bit; 853 } else { 854 cfg &= sc->sc_suspend ? bit : 0; 855 } 856 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg); 857 858 return true; 859 } 860 861 bool 862 dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual) 863 { 864 865 return dbcool_do_pmf(dev, qual, true); 866 } 867 868 bool 869 dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual) 870 { 871 872 return dbcool_do_pmf(dev, qual, false); 873 } 874 875 uint8_t 876 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg) 877 { 878 uint8_t data = 0; 879 880 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 881 return data; 882 883 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) { 884 /* ADM1027 doesn't support i2c read_byte protocol */ 885 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0) 886 goto bad; 887 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0); 888 } else 889 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data, 890 0); 891 892 bad: 893 iic_release_bus(dc->dc_tag, 0); 894 return data; 895 } 896 897 void 898 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val) 899 { 900 if (iic_acquire_bus(dc->dc_tag, 0) != 0) 901 return; 902 903 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0); 904 905 iic_release_bus(dc->dc_tag, 0); 906 } 907 908 static bool 909 dbcool_islocked(struct dbcool_softc *sc) 910 { 911 uint8_t cfg_reg; 912 913 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 914 return 0; 915 916 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 917 cfg_reg = DBCOOL_ADT7466_CONFIG1; 918 else 919 cfg_reg = DBCOOL_CONFIG1_REG; 920 921 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK) 922 return 1; 923 else 924 return 0; 925 } 926 927 static int 928 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres) 929 { 930 uint8_t t1, t2, t3, val, ext = 0; 931 int temp; 932 933 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 934 /* 935 * ADT7466 temps are in strange location 936 */ 937 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1); 938 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 939 if (extres) 940 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 941 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 942 /* 943 * ADM1030 temps are in their own special place, too 944 */ 945 if (extres) { 946 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES); 947 if (reg == DBCOOL_ADM1030_L_TEMP) 948 ext >>= 6; 949 else if (reg == DBCOOL_ADM1031_R2_TEMP) 950 ext >>= 4; 951 else 952 ext >>= 1; 953 ext &= 0x03; 954 } 955 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 956 } else if (extres) { 957 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG); 958 959 /* Read all msb regs to unlatch them */ 960 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN); 961 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP); 962 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP); 963 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP); 964 switch (reg) { 965 case DBCOOL_REMOTE1_TEMP: 966 val = t1; 967 ext >>= 2; 968 break; 969 case DBCOOL_LOCAL_TEMP: 970 val = t3; 971 ext >>= 4; 972 break; 973 case DBCOOL_REMOTE2_TEMP: 974 val = t2; 975 ext >>= 6; 976 break; 977 default: 978 val = 0; 979 break; 980 } 981 ext &= 0x03; 982 } 983 else 984 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 985 986 /* Check for invalid temp values */ 987 if ((sc->sc_temp_offset == 0 && val == 0x80) || 988 (sc->sc_temp_offset != 0 && val == 0)) 989 return 0; 990 991 /* If using offset mode, adjust, else treat as signed */ 992 if (sc->sc_temp_offset) { 993 temp = val; 994 temp -= sc->sc_temp_offset; 995 } else 996 temp = (int8_t)val; 997 998 /* Convert degC to uK and include extended precision bits */ 999 temp *= 1000000; 1000 temp += 250000 * (int)ext; 1001 temp += 273150000U; 1002 1003 return temp; 1004 } 1005 1006 static int 1007 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg) 1008 { 1009 int rpm; 1010 uint8_t rpm_lo, rpm_hi; 1011 1012 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1013 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1014 rpm_hi = (rpm_lo == 0xff)?0xff:0x0; 1015 else 1016 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1); 1017 1018 rpm = (rpm_hi << 8) | rpm_lo; 1019 if (rpm == 0xffff) 1020 return 0; /* 0xffff indicates stalled/failed fan */ 1021 1022 /* don't divide by zero */ 1023 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm); 1024 } 1025 1026 /* Provide chip's supply voltage, in microvolts */ 1027 static int 1028 dbcool_supply_voltage(struct dbcool_softc *sc) 1029 { 1030 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) { 1031 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc) 1032 return 5002500; 1033 else 1034 return 3300000; 1035 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1036 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 1037 DBCOOL_ADT7466_CFG1_Vcc) 1038 return 5000000; 1039 else 1040 return 3300000; 1041 } else 1042 return 3300000; 1043 } 1044 1045 /* 1046 * Nominal voltages are calculated in microvolts 1047 */ 1048 static int 1049 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres) 1050 { 1051 uint8_t ext = 0, v1, v2, v3, v4, val; 1052 int64_t ret; 1053 int64_t nom; 1054 1055 nom = nominal_voltages[nom_idx]; 1056 if (nom < 0) 1057 nom = sc->sc_supply_voltage; 1058 1059 /* ADT7466 voltages are in strange locations with only 8-bits */ 1060 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1061 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1062 else 1063 /* 1064 * It's a "normal" dbCool chip - check for regs that 1065 * share extended resolution bits since we have to 1066 * read all the MSB registers to unlatch them. 1067 */ 1068 if (!extres) 1069 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1070 else if (reg == DBCOOL_12VIN) { 1071 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03; 1072 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg); 1073 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true); 1074 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) { 1075 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON); 1076 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON); 1077 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT); 1078 if (reg == DBCOOL_IMON) { 1079 val = v1; 1080 ext >>= 6; 1081 } else { 1082 val = v2; 1083 ext >>= 4; 1084 } 1085 ext &= 0x0f; 1086 } else { 1087 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG); 1088 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN); 1089 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP); 1090 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC); 1091 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN); 1092 1093 switch (reg) { 1094 case DBCOOL_25VIN: 1095 val = v1; 1096 break; 1097 case DBCOOL_VCCP: 1098 val = v2; 1099 ext >>= 2; 1100 break; 1101 case DBCOOL_VCC: 1102 val = v3; 1103 ext >>= 4; 1104 break; 1105 case DBCOOL_5VIN: 1106 val = v4; 1107 ext >>= 6; 1108 break; 1109 default: 1110 val = nom = 0; 1111 } 1112 ext &= 0x03; 1113 } 1114 1115 /* 1116 * Scale the nominal value by the 10-bit fraction 1117 * 1118 * Returned value is in microvolts. 1119 */ 1120 ret = val; 1121 ret <<= 2; 1122 ret |= ext; 1123 ret = (ret * nom) / 0x300; 1124 1125 return ret; 1126 } 1127 1128 static int 1129 sysctl_dbcool_temp(SYSCTLFN_ARGS) 1130 { 1131 struct sysctlnode node; 1132 struct dbcool_softc *sc; 1133 int reg, error; 1134 uint8_t chipreg; 1135 uint8_t newreg; 1136 1137 node = *rnode; 1138 sc = (struct dbcool_softc *)node.sysctl_data; 1139 chipreg = node.sysctl_num & 0xff; 1140 1141 if (sc->sc_temp_offset) { 1142 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1143 reg -= sc->sc_temp_offset; 1144 } else 1145 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1146 1147 node.sysctl_data = ® 1148 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1149 1150 if (error || newp == NULL) 1151 return error; 1152 1153 /* We were asked to update the value - sanity check before writing */ 1154 if (*(int *)node.sysctl_data < -64 || 1155 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset) 1156 return EINVAL; 1157 1158 newreg = *(int *)node.sysctl_data; 1159 newreg += sc->sc_temp_offset; 1160 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1161 return 0; 1162 } 1163 1164 static int 1165 sysctl_adm1030_temp(SYSCTLFN_ARGS) 1166 { 1167 struct sysctlnode node; 1168 struct dbcool_softc *sc; 1169 int reg, error; 1170 uint8_t chipreg, oldreg, newreg; 1171 1172 node = *rnode; 1173 sc = (struct dbcool_softc *)node.sysctl_data; 1174 chipreg = node.sysctl_num & 0xff; 1175 1176 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1177 reg = (oldreg >> 1) & ~0x03; 1178 1179 node.sysctl_data = ® 1180 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1181 1182 if (error || newp == NULL) 1183 return error; 1184 1185 /* We were asked to update the value - sanity check before writing */ 1186 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127) 1187 return EINVAL; 1188 1189 newreg = *(int *)node.sysctl_data; 1190 newreg &= ~0x03; 1191 newreg <<= 1; 1192 newreg |= (oldreg & 0x07); 1193 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1194 return 0; 1195 } 1196 1197 static int 1198 sysctl_adm1030_trange(SYSCTLFN_ARGS) 1199 { 1200 struct sysctlnode node; 1201 struct dbcool_softc *sc; 1202 int reg, error, newval; 1203 uint8_t chipreg, oldreg, newreg; 1204 1205 node = *rnode; 1206 sc = (struct dbcool_softc *)node.sysctl_data; 1207 chipreg = node.sysctl_num & 0xff; 1208 1209 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1210 reg = oldreg & 0x07; 1211 1212 node.sysctl_data = ® 1213 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1214 1215 if (error || newp == NULL) 1216 return error; 1217 1218 /* We were asked to update the value - sanity check before writing */ 1219 newval = *(int *)node.sysctl_data; 1220 1221 if (newval == 5) 1222 newreg = 0; 1223 else if (newval == 10) 1224 newreg = 1; 1225 else if (newval == 20) 1226 newreg = 2; 1227 else if (newval == 40) 1228 newreg = 3; 1229 else if (newval == 80) 1230 newreg = 4; 1231 else 1232 return EINVAL; 1233 1234 newreg |= (oldreg & ~0x07); 1235 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1236 return 0; 1237 } 1238 1239 static int 1240 sysctl_dbcool_duty(SYSCTLFN_ARGS) 1241 { 1242 struct sysctlnode node; 1243 struct dbcool_softc *sc; 1244 int reg, error; 1245 uint8_t chipreg, oldreg, newreg; 1246 1247 node = *rnode; 1248 sc = (struct dbcool_softc *)node.sysctl_data; 1249 chipreg = node.sysctl_num & 0xff; 1250 1251 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1252 reg = (uint32_t)oldreg; 1253 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1254 reg = ((reg & 0x0f) * 100) / 15; 1255 else 1256 reg = (reg * 100) / 255; 1257 node.sysctl_data = ® 1258 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1259 1260 if (error || newp == NULL) 1261 return error; 1262 1263 /* We were asked to update the value - sanity check before writing */ 1264 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100) 1265 return EINVAL; 1266 1267 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1268 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100; 1269 newreg |= oldreg & 0xf0; 1270 } else 1271 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100; 1272 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1273 return 0; 1274 } 1275 1276 static int 1277 sysctl_dbcool_behavior(SYSCTLFN_ARGS) 1278 { 1279 struct sysctlnode node; 1280 struct dbcool_softc *sc; 1281 int i, reg, error; 1282 uint8_t chipreg, oldreg, newreg; 1283 1284 node = *rnode; 1285 sc = (struct dbcool_softc *)node.sysctl_data; 1286 chipreg = node.sysctl_num & 0xff; 1287 1288 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1289 1290 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1291 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0) 1292 reg = 4; 1293 else if ((oldreg & 0x80) == 0) 1294 reg = 7; 1295 else if ((oldreg & 0x60) == 0) 1296 reg = 4; 1297 else 1298 reg = 6; 1299 } else 1300 reg = (oldreg >> 5) & 0x07; 1301 1302 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav)); 1303 node.sysctl_data = dbcool_cur_behav; 1304 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1305 1306 if (error || newp == NULL) 1307 return error; 1308 1309 /* We were asked to update the value - convert string to value */ 1310 newreg = __arraycount(behavior); 1311 for (i = 0; i < __arraycount(behavior); i++) 1312 if (strcmp(node.sysctl_data, behavior[i]) == 0) 1313 break; 1314 if (i >= __arraycount(behavior)) 1315 return EINVAL; 1316 newreg = i; 1317 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) { 1318 /* 1319 * ADM1030 splits fan controller behavior across two 1320 * registers. We also do not support Auto-Filter mode 1321 * nor do we support Manual-RPM-feedback. 1322 */ 1323 if (newreg == 4) { 1324 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2); 1325 oldreg &= ~0x01; 1326 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1327 } else { 1328 if (newreg == 0) 1329 newreg = 4; 1330 else if (newreg == 6) 1331 newreg = 7; 1332 else if (newreg == 7) 1333 newreg = 0; 1334 else 1335 return EINVAL; 1336 newreg <<= 5; 1337 newreg |= (oldreg & 0x1f); 1338 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1339 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1; 1340 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg); 1341 } 1342 } else { 1343 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5); 1344 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1345 } 1346 return 0; 1347 } 1348 1349 static int 1350 sysctl_dbcool_slope(SYSCTLFN_ARGS) 1351 { 1352 struct sysctlnode node; 1353 struct dbcool_softc *sc; 1354 int reg, error; 1355 uint8_t chipreg; 1356 uint8_t newreg; 1357 1358 node = *rnode; 1359 sc = (struct dbcool_softc *)node.sysctl_data; 1360 chipreg = node.sysctl_num & 0xff; 1361 1362 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f; 1363 node.sysctl_data = ® 1364 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1365 1366 if (error || newp == NULL) 1367 return error; 1368 1369 /* We were asked to update the value - sanity check before writing */ 1370 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f) 1371 return EINVAL; 1372 1373 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) | 1374 (*(int *)node.sysctl_data << 4); 1375 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1376 return 0; 1377 } 1378 1379 static int 1380 sysctl_dbcool_thyst(SYSCTLFN_ARGS) 1381 { 1382 struct sysctlnode node; 1383 struct dbcool_softc *sc; 1384 int reg, error; 1385 uint8_t chipreg; 1386 uint8_t newreg, newhyst; 1387 1388 node = *rnode; 1389 sc = (struct dbcool_softc *)node.sysctl_data; 1390 chipreg = node.sysctl_num & 0x7f; 1391 1392 /* retrieve 4-bit value */ 1393 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1394 if ((node.sysctl_num & 0x80) == 0) 1395 reg = newreg >> 4; 1396 else 1397 reg = newreg; 1398 reg = reg & 0x0f; 1399 1400 node.sysctl_data = ® 1401 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1402 1403 if (error || newp == NULL) 1404 return error; 1405 1406 /* We were asked to update the value - sanity check before writing */ 1407 newhyst = *(int *)node.sysctl_data; 1408 if (newhyst > 0x0f) 1409 return EINVAL; 1410 1411 /* Insert new value into field and update register */ 1412 if ((node.sysctl_num & 0x80) == 0) { 1413 newreg &= 0x0f; 1414 newreg |= (newhyst << 4); 1415 } else { 1416 newreg &= 0xf0; 1417 newreg |= newhyst; 1418 } 1419 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1420 return 0; 1421 } 1422 1423 #ifdef DBCOOL_DEBUG 1424 1425 /* 1426 * These routines can be used for debugging. reg_select is used to 1427 * select any arbitrary register in the device. reg_access is used 1428 * to read (and optionally update) the selected register. 1429 * 1430 * No attempt is made to validate the data passed. If you use these 1431 * routines, you are assumed to know what you're doing! 1432 * 1433 * Caveat user 1434 */ 1435 static int 1436 sysctl_dbcool_reg_select(SYSCTLFN_ARGS) 1437 { 1438 struct sysctlnode node; 1439 struct dbcool_softc *sc; 1440 int reg, error; 1441 1442 node = *rnode; 1443 sc = (struct dbcool_softc *)node.sysctl_data; 1444 1445 reg = sc->sc_user_reg; 1446 node.sysctl_data = ® 1447 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1448 1449 if (error || newp == NULL) 1450 return error; 1451 1452 sc->sc_user_reg = *(int *)node.sysctl_data; 1453 return 0; 1454 } 1455 1456 static int 1457 sysctl_dbcool_reg_access(SYSCTLFN_ARGS) 1458 { 1459 struct sysctlnode node; 1460 struct dbcool_softc *sc; 1461 int reg, error; 1462 uint8_t chipreg; 1463 uint8_t newreg; 1464 1465 node = *rnode; 1466 sc = (struct dbcool_softc *)node.sysctl_data; 1467 chipreg = sc->sc_user_reg; 1468 1469 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg); 1470 node.sysctl_data = ® 1471 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1472 1473 if (error || newp == NULL) 1474 return error; 1475 1476 newreg = *(int *)node.sysctl_data; 1477 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg); 1478 return 0; 1479 } 1480 #endif /* DBCOOL_DEBUG */ 1481 1482 /* 1483 * Encode an index number and register number for use as a sysctl_num 1484 * so we can select the correct device register later. 1485 */ 1486 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg) 1487 1488 void 1489 dbcool_setup(device_t self) 1490 { 1491 struct dbcool_softc *sc = device_private(self); 1492 const struct sysctlnode *me = NULL; 1493 #ifdef DBCOOL_DEBUG 1494 struct sysctlnode *node = NULL; 1495 #endif 1496 uint8_t cfg_val, cfg_reg; 1497 int ret, error; 1498 1499 /* 1500 * Some chips are capable of reporting an extended temperature range 1501 * by default. On these models, config register 5 bit 0 can be set 1502 * to 1 for compatibility with other chips that report 2s complement. 1503 */ 1504 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) { 1505 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80) 1506 sc->sc_temp_offset = 64; 1507 else 1508 sc->sc_temp_offset = 0; 1509 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) { 1510 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) & 1511 DBCOOL_CFG5_TWOSCOMP) 1512 sc->sc_temp_offset = 0; 1513 else 1514 sc->sc_temp_offset = 64; 1515 } else 1516 sc->sc_temp_offset = 0; 1517 1518 /* Determine Vcc for this chip */ 1519 sc->sc_supply_voltage = dbcool_supply_voltage(sc); 1520 1521 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me, 1522 CTLFLAG_READWRITE, 1523 CTLTYPE_NODE, device_xname(self), NULL, 1524 NULL, 0, NULL, 0, 1525 CTL_HW, CTL_CREATE, CTL_EOL); 1526 if (ret == 0) 1527 sc->sc_root_sysctl_num = me->sysctl_num; 1528 else 1529 sc->sc_root_sysctl_num = 0; 1530 1531 aprint_debug_dev(self, 1532 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n", 1533 sc->sc_supply_voltage / 1000000, 1534 sc->sc_supply_voltage % 1000000, 1535 sc->sc_temp_offset ? "extended" : "normal"); 1536 1537 /* Create the sensors for this device */ 1538 sc->sc_sme = sysmon_envsys_create(); 1539 if (dbcool_setup_sensors(sc)) 1540 goto out; 1541 1542 if (sc->sc_root_sysctl_num != 0) { 1543 /* If supported, create sysctl tree for fan PWM controllers */ 1544 if (sc->sc_dc.dc_chip->power != NULL) 1545 dbcool_setup_controllers(sc); 1546 1547 #ifdef DBCOOL_DEBUG 1548 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1549 (void *)&node, 1550 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL, 1551 sysctl_dbcool_reg_select, 1552 0, (void *)sc, sizeof(int), 1553 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1554 if (node != NULL) 1555 node->sysctl_data = sc; 1556 1557 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, 1558 (void *)&node, 1559 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL, 1560 sysctl_dbcool_reg_access, 1561 0, (void *)sc, sizeof(int), 1562 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL); 1563 if (node != NULL) 1564 node->sysctl_data = sc; 1565 #endif /* DBCOOL_DEBUG */ 1566 } 1567 1568 /* 1569 * Read and rewrite config register to activate device 1570 */ 1571 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 1572 cfg_reg = DBCOOL_ADM1030_CFG1; 1573 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) 1574 cfg_reg = DBCOOL_ADT7466_CONFIG1; 1575 else 1576 cfg_reg = DBCOOL_CONFIG1_REG; 1577 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG); 1578 if ((cfg_val & DBCOOL_CFG1_START) == 0) { 1579 cfg_val |= DBCOOL_CFG1_START; 1580 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val); 1581 } 1582 if (dbcool_islocked(sc)) 1583 aprint_normal_dev(self, "configuration locked\n"); 1584 1585 sc->sc_sme->sme_name = device_xname(self); 1586 sc->sc_sme->sme_cookie = sc; 1587 sc->sc_sme->sme_refresh = dbcool_refresh; 1588 sc->sc_sme->sme_set_limits = dbcool_set_limits; 1589 sc->sc_sme->sme_get_limits = dbcool_get_limits; 1590 1591 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) { 1592 aprint_error_dev(self, 1593 "unable to register with sysmon (%d)\n", error); 1594 goto out; 1595 } 1596 1597 return; 1598 1599 out: 1600 sysmon_envsys_destroy(sc->sc_sme); 1601 sc->sc_sme = NULL; 1602 } 1603 1604 static int 1605 dbcool_setup_sensors(struct dbcool_softc *sc) 1606 { 1607 int i; 1608 int error = 0; 1609 uint8_t vid_reg, vid_val; 1610 struct chip_id *chip = sc->sc_dc.dc_chip; 1611 1612 for (i=0; chip->table[i].type != DBC_EOF; i++) { 1613 if (i < DBCOOL_MAXSENSORS) 1614 sc->sc_sysctl_num[i] = -1; 1615 else if (chip->table[i].type != DBC_CTL) { 1616 aprint_normal_dev(sc->sc_dev, "chip table too big!\n"); 1617 break; 1618 } 1619 switch (chip->table[i].type) { 1620 case DBC_TEMP: 1621 sc->sc_sensor[i].units = ENVSYS_STEMP; 1622 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1623 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1624 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1625 error = dbcool_attach_sensor(sc, i); 1626 break; 1627 case DBC_VOLT: 1628 /* 1629 * If 12V-In pin has been reconfigured as 6th bit 1630 * of VID code, don't create a 12V-In sensor 1631 */ 1632 if ((chip->flags & DBCFLAG_HAS_VID_SEL) && 1633 (chip->table[i].reg.val_reg == DBCOOL_12VIN) && 1634 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) & 1635 0x80)) 1636 break; 1637 1638 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 1639 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1640 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1641 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1642 error = dbcool_attach_sensor(sc, i); 1643 break; 1644 case DBC_FAN: 1645 sc->sc_sensor[i].units = ENVSYS_SFANRPM; 1646 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1647 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS; 1648 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY; 1649 error = dbcool_attach_sensor(sc, i); 1650 break; 1651 case DBC_VID: 1652 sc->sc_sensor[i].units = ENVSYS_INTEGER; 1653 sc->sc_sensor[i].state = ENVSYS_SINVALID; 1654 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP; 1655 1656 /* retrieve 5- or 6-bit value */ 1657 vid_reg = chip->table[i].reg.val_reg; 1658 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg); 1659 if (chip->flags & DBCFLAG_HAS_VID_SEL) 1660 vid_val &= 0x3f; 1661 else 1662 vid_val &= 0x1f; 1663 sc->sc_sensor[i].value_cur = vid_val; 1664 1665 error = dbcool_attach_sensor(sc, i); 1666 break; 1667 case DBC_CTL: 1668 error = dbcool_attach_temp_control(sc, i, chip); 1669 if (error) { 1670 aprint_error_dev(sc->sc_dev, 1671 "attach index %d failed %d\n", 1672 i, error); 1673 error = 0; 1674 } 1675 break; 1676 default: 1677 aprint_error_dev(sc->sc_dev, 1678 "sensor_table index %d has bad type %d\n", 1679 i, chip->table[i].type); 1680 break; 1681 } 1682 if (error) 1683 break; 1684 } 1685 return error; 1686 } 1687 1688 static int 1689 dbcool_attach_sensor(struct dbcool_softc *sc, int idx) 1690 { 1691 int name_index; 1692 int error = 0; 1693 char name[8]; 1694 1695 name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1696 snprintf(name, 7, "s%02x", sc->sc_dc.dc_chip->table[idx].reg.val_reg); 1697 if (device_getprop_string(sc->sc_dev, name, sc->sc_sensor[idx].desc, 1698 sizeof(sc->sc_sensor[idx].desc)) < 0) { 1699 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index], 1700 sizeof(sc->sc_sensor[idx].desc)); 1701 } 1702 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg; 1703 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index; 1704 1705 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]); 1706 return error; 1707 } 1708 1709 static int 1710 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx, 1711 struct chip_id *chip) 1712 { 1713 const struct sysctlnode *me2 = NULL, *node; 1714 int j, ret, sysctl_index, rw_flag; 1715 uint8_t sysctl_reg; 1716 char name[SYSCTL_NAMELEN]; 1717 1718 /* Search for the corresponding temp sensor */ 1719 for (j = 0; j < idx; j++) { 1720 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP) 1721 continue; 1722 if (chip->table[j].name_index == chip->table[idx].name_index) 1723 break; 1724 } 1725 if (j >= idx) /* Temp sensor not found */ 1726 return ENOENT; 1727 1728 /* create sysctl node for the sensor if not one already there */ 1729 if (sc->sc_sysctl_num[j] == -1) { 1730 int name_index = sc->sc_dc.dc_chip->table[idx].name_index; 1731 1732 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1733 CTLFLAG_READWRITE, 1734 CTLTYPE_NODE, dbc_sensor_names[name_index], 1735 sc->sc_sensor[j].desc, 1736 NULL, 0, NULL, 0, 1737 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, 1738 CTL_EOL); 1739 if (me2 != NULL) 1740 sc->sc_sysctl_num[j] = me2->sysctl_num; 1741 else 1742 return ret; 1743 } 1744 /* add sysctl leaf node for this control variable */ 1745 sysctl_index = chip->table[idx].sysctl_index; 1746 sysctl_reg = chip->table[idx].reg.val_reg; 1747 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name)); 1748 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc)) 1749 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1750 else 1751 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1752 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag, 1753 CTLTYPE_INT, name, 1754 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc), 1755 dbc_sysctl_table[sysctl_index].helper, 1756 0, (void *)sc, sizeof(int), 1757 CTL_HW, sc->sc_root_sysctl_num, 1758 sc->sc_sysctl_num[j], 1759 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL); 1760 1761 return ret; 1762 } 1763 1764 static void 1765 dbcool_setup_controllers(struct dbcool_softc *sc) 1766 { 1767 int i, j, rw_flag; 1768 uint8_t sysctl_reg; 1769 struct chip_id *chip = sc->sc_dc.dc_chip; 1770 const struct sysctlnode *me2 = NULL; 1771 const struct sysctlnode *node = NULL; 1772 char name[SYSCTL_NAMELEN]; 1773 1774 for (i = 0; chip->power[i].desc != NULL; i++) { 1775 snprintf(name, sizeof(name), "fan_ctl_%d", i); 1776 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2, 1777 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 1778 CTLTYPE_NODE, name, NULL, 1779 NULL, 0, NULL, 0, 1780 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL); 1781 1782 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) { 1783 if (j == DBC_PWM_MAX_DUTY && 1784 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0) 1785 continue; 1786 sysctl_reg = chip->power[i].power_regs[j]; 1787 if (sysctl_reg == DBCOOL_NO_REG) 1788 continue; 1789 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name)); 1790 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc)) 1791 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC; 1792 else 1793 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC; 1794 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL, 1795 &node, rw_flag, 1796 (j == DBC_PWM_BEHAVIOR)? 1797 CTLTYPE_STRING:CTLTYPE_INT, 1798 name, 1799 SYSCTL_DESCR(dbc_sysctl_table[j].desc), 1800 dbc_sysctl_table[j].helper, 1801 0, sc, 1802 ( j == DBC_PWM_BEHAVIOR)? 1803 sizeof(dbcool_cur_behav): sizeof(int), 1804 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num, 1805 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL); 1806 } 1807 } 1808 } 1809 1810 static void 1811 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1812 { 1813 struct dbcool_softc *sc=sme->sme_cookie; 1814 int i, nom_volt_idx, cur; 1815 struct reg_list *reg; 1816 1817 i = edata->sensor; 1818 reg = sc->sc_regs[i]; 1819 1820 edata->state = ENVSYS_SVALID; 1821 switch (edata->units) 1822 { 1823 case ENVSYS_STEMP: 1824 cur = dbcool_read_temp(sc, reg->val_reg, true); 1825 break; 1826 case ENVSYS_SVOLTS_DC: 1827 nom_volt_idx = sc->sc_nom_volt[i]; 1828 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx, 1829 true); 1830 break; 1831 case ENVSYS_SFANRPM: 1832 cur = dbcool_read_rpm(sc, reg->val_reg); 1833 break; 1834 case ENVSYS_INTEGER: 1835 return; 1836 default: 1837 edata->state = ENVSYS_SINVALID; 1838 return; 1839 } 1840 1841 if (cur == 0 && (edata->units != ENVSYS_SFANRPM)) 1842 edata->state = ENVSYS_SINVALID; 1843 1844 /* 1845 * If fan is "stalled" but has no low limit, treat 1846 * it as though the fan is not installed. 1847 */ 1848 else if (edata->units == ENVSYS_SFANRPM && cur == 0 && 1849 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN))) 1850 edata->state = ENVSYS_SINVALID; 1851 1852 edata->value_cur = cur; 1853 } 1854 1855 int 1856 dbcool_chip_ident(struct dbcool_chipset *dc) 1857 { 1858 /* verify this is a supported dbCool chip */ 1859 uint8_t c_id, d_id, r_id; 1860 int i; 1861 1862 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1863 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1864 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1865 1866 /* The EMC6D103S only supports read_byte and since dc->dc_chip is 1867 * NULL when we call dc->dc_readreg above we use 1868 * send_byte/receive_byte which doesn't work. 1869 * 1870 * So if we only get 0's back then try again with dc->dc_chip 1871 * set to the EMC6D103S_DEVICEID and which doesn't have 1872 * DBCFLAG_NO_READBYTE set so read_byte will be used 1873 */ 1874 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) { 1875 for (i = 0; chip_table[i].company != 0; i++) 1876 if ((SMSC_COMPANYID == chip_table[i].company) && 1877 (EMC6D103S_DEVICEID == chip_table[i].device)) { 1878 dc->dc_chip = &chip_table[i]; 1879 break; 1880 } 1881 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG); 1882 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG); 1883 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG); 1884 } 1885 1886 for (i = 0; chip_table[i].company != 0; i++) 1887 if ((c_id == chip_table[i].company) && 1888 (d_id == chip_table[i].device || 1889 chip_table[i].device == 0xff) && 1890 (r_id == chip_table[i].rev || 1891 chip_table[i].rev == 0xff)) { 1892 dc->dc_chip = &chip_table[i]; 1893 return i; 1894 } 1895 1896 aprint_debug("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x" 1897 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id, 1898 r_id); 1899 1900 return -1; 1901 } 1902 1903 /* 1904 * Retrieve sensor limits from the chip registers 1905 */ 1906 static void 1907 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 1908 sysmon_envsys_lim_t *limits, uint32_t *props) 1909 { 1910 int index = edata->sensor; 1911 struct dbcool_softc *sc = sme->sme_cookie; 1912 1913 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1914 switch (edata->units) { 1915 case ENVSYS_STEMP: 1916 dbcool_get_temp_limits(sc, index, limits, props); 1917 break; 1918 case ENVSYS_SVOLTS_DC: 1919 dbcool_get_volt_limits(sc, index, limits, props); 1920 break; 1921 case ENVSYS_SFANRPM: 1922 dbcool_get_fan_limits(sc, index, limits, props); 1923 1924 /* FALLTHROUGH */ 1925 default: 1926 break; 1927 } 1928 *props &= ~PROP_DRIVER_LIMITS; 1929 1930 /* If both limits provided, make sure they're sane */ 1931 if ((*props & PROP_CRITMIN) && 1932 (*props & PROP_CRITMAX) && 1933 (limits->sel_critmin >= limits->sel_critmax)) 1934 *props &= ~(PROP_CRITMIN | PROP_CRITMAX); 1935 1936 /* 1937 * If this is the first time through, save these values 1938 * in case user overrides them and then requests a reset. 1939 */ 1940 if (sc->sc_defprops[index] == 0) { 1941 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS; 1942 sc->sc_deflims[index] = *limits; 1943 } 1944 } 1945 1946 static void 1947 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx, 1948 sysmon_envsys_lim_t *lims, uint32_t *props) 1949 { 1950 struct reg_list *reg = sc->sc_regs[idx]; 1951 uint8_t lo_lim, hi_lim; 1952 1953 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1954 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 1955 1956 if (sc->sc_temp_offset) { 1957 if (lo_lim > 0x01) { 1958 lims->sel_critmin = lo_lim - sc->sc_temp_offset; 1959 *props |= PROP_CRITMIN; 1960 } 1961 if (hi_lim != 0xff) { 1962 lims->sel_critmax = hi_lim - sc->sc_temp_offset; 1963 *props |= PROP_CRITMAX; 1964 } 1965 } else { 1966 if (lo_lim != 0x80 && lo_lim != 0x81) { 1967 lims->sel_critmin = (int8_t)lo_lim; 1968 *props |= PROP_CRITMIN; 1969 } 1970 1971 if (hi_lim != 0x7f) { 1972 lims->sel_critmax = (int8_t)hi_lim; 1973 *props |= PROP_CRITMAX; 1974 } 1975 } 1976 1977 /* Convert temp limits to microKelvin */ 1978 lims->sel_critmin *= 1000000; 1979 lims->sel_critmin += 273150000; 1980 lims->sel_critmax *= 1000000; 1981 lims->sel_critmax += 273150000; 1982 } 1983 1984 static void 1985 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx, 1986 sysmon_envsys_lim_t *lims, uint32_t *props) 1987 { 1988 struct reg_list *reg = sc->sc_regs[idx]; 1989 int64_t limit; 1990 int nom; 1991 1992 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 1993 if (nom < 0) 1994 nom = dbcool_supply_voltage(sc); 1995 nom *= 1000000; /* scale for microvolts */ 1996 1997 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg); 1998 if (limit != 0x00 && limit != 0xff) { 1999 limit *= nom; 2000 limit /= 0xc0; 2001 lims->sel_critmin = limit; 2002 *props |= PROP_CRITMIN; 2003 } 2004 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg); 2005 if (limit != 0x00 && limit != 0xff) { 2006 limit *= nom; 2007 limit /= 0xc0; 2008 lims->sel_critmax = limit; 2009 *props |= PROP_CRITMAX; 2010 } 2011 } 2012 2013 static void 2014 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx, 2015 sysmon_envsys_lim_t *lims, uint32_t *props) 2016 { 2017 struct reg_list *reg = sc->sc_regs[idx]; 2018 int32_t limit; 2019 2020 limit = dbcool_read_rpm(sc, reg->lo_lim_reg); 2021 if (limit) { 2022 lims->sel_critmin = limit; 2023 *props |= PROP_CRITMIN; 2024 } 2025 } 2026 2027 /* 2028 * Update sensor limits in the chip registers 2029 */ 2030 static void 2031 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata, 2032 sysmon_envsys_lim_t *limits, uint32_t *props) 2033 { 2034 int index = edata->sensor; 2035 struct dbcool_softc *sc = sme->sme_cookie; 2036 2037 if (limits == NULL) { 2038 limits = &sc->sc_deflims[index]; 2039 props = &sc->sc_defprops[index]; 2040 } 2041 switch (edata->units) { 2042 case ENVSYS_STEMP: 2043 dbcool_set_temp_limits(sc, index, limits, props); 2044 break; 2045 case ENVSYS_SVOLTS_DC: 2046 dbcool_set_volt_limits(sc, index, limits, props); 2047 break; 2048 case ENVSYS_SFANRPM: 2049 dbcool_set_fan_limits(sc, index, limits, props); 2050 2051 /* FALLTHROUGH */ 2052 default: 2053 break; 2054 } 2055 *props &= ~PROP_DRIVER_LIMITS; 2056 } 2057 2058 static void 2059 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx, 2060 sysmon_envsys_lim_t *lims, uint32_t *props) 2061 { 2062 struct reg_list *reg = sc->sc_regs[idx]; 2063 int32_t limit; 2064 2065 if (*props & PROP_CRITMIN) { 2066 limit = lims->sel_critmin - 273150000; 2067 limit /= 1000000; 2068 if (sc->sc_temp_offset) { 2069 limit += sc->sc_temp_offset; 2070 if (limit < 0) 2071 limit = 0; 2072 else if (limit > 255) 2073 limit = 255; 2074 } else { 2075 if (limit < -127) 2076 limit = -127; 2077 else if (limit > 127) 2078 limit = 127; 2079 } 2080 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2081 (uint8_t)limit); 2082 } else if (*props & PROP_DRIVER_LIMITS) { 2083 if (sc->sc_temp_offset) 2084 limit = 0x00; 2085 else 2086 limit = 0x80; 2087 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2088 (uint8_t)limit); 2089 } 2090 2091 if (*props & PROP_CRITMAX) { 2092 limit = lims->sel_critmax - 273150000; 2093 limit /= 1000000; 2094 if (sc->sc_temp_offset) { 2095 limit += sc->sc_temp_offset; 2096 if (limit < 0) 2097 limit = 0; 2098 else if (limit > 255) 2099 limit = 255; 2100 } else { 2101 if (limit < -127) 2102 limit = -127; 2103 else if (limit > 127) 2104 limit = 127; 2105 } 2106 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2107 (uint8_t)limit); 2108 } else if (*props & PROP_DRIVER_LIMITS) { 2109 if (sc->sc_temp_offset) 2110 limit = 0xff; 2111 else 2112 limit = 0x7f; 2113 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 2114 (uint8_t)limit); 2115 } 2116 } 2117 2118 static void 2119 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx, 2120 sysmon_envsys_lim_t *lims, uint32_t *props) 2121 { 2122 struct reg_list *reg = sc->sc_regs[idx]; 2123 int64_t limit; 2124 int nom; 2125 2126 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index]; 2127 if (nom < 0) 2128 nom = dbcool_supply_voltage(sc); 2129 nom *= 1000000; /* scale for microvolts */ 2130 2131 if (*props & PROP_CRITMIN) { 2132 limit = lims->sel_critmin; 2133 limit *= 0xc0; 2134 limit /= nom; 2135 if (limit > 0xff) 2136 limit = 0xff; 2137 else if (limit < 0) 2138 limit = 0; 2139 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit); 2140 } else if (*props & PROP_DRIVER_LIMITS) 2141 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0); 2142 2143 if (*props & PROP_CRITMAX) { 2144 limit = lims->sel_critmax; 2145 limit *= 0xc0; 2146 limit /= nom; 2147 if (limit > 0xff) 2148 limit = 0xff; 2149 else if (limit < 0) 2150 limit = 0; 2151 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit); 2152 } else if (*props & PROP_DRIVER_LIMITS) 2153 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff); 2154 } 2155 2156 static void 2157 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx, 2158 sysmon_envsys_lim_t *lims, uint32_t *props) 2159 { 2160 struct reg_list *reg = sc->sc_regs[idx]; 2161 int32_t limit, dividend; 2162 2163 if (*props & PROP_CRITMIN) { 2164 limit = lims->sel_critmin; 2165 if (limit == 0) 2166 limit = 0xffff; 2167 else { 2168 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) 2169 dividend = 11250 * 60; 2170 else 2171 dividend = 90000 * 60; 2172 limit = limit / dividend; 2173 if (limit > 0xffff) 2174 limit = 0xffff; 2175 } 2176 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 2177 limit & 0xff); 2178 limit >>= 8; 2179 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 2180 limit & 0xff); 2181 } else if (*props & PROP_DRIVER_LIMITS) { 2182 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff); 2183 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff); 2184 } 2185 } 2186 2187 MODULE(MODULE_CLASS_DRIVER, dbcool, "iic,sysmon_envsys"); 2188 2189 #ifdef _MODULE 2190 #include "ioconf.c" 2191 #endif 2192 2193 static int 2194 dbcool_modcmd(modcmd_t cmd, void *opaque) 2195 { 2196 int error = 0; 2197 #ifdef _MODULE 2198 static struct sysctllog *dbcool_sysctl_clog; 2199 #endif 2200 2201 switch (cmd) { 2202 case MODULE_CMD_INIT: 2203 #ifdef _MODULE 2204 error = config_init_component(cfdriver_ioconf_dbcool, 2205 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2206 sysctl_dbcoolsetup(&dbcool_sysctl_clog); 2207 #endif 2208 return error; 2209 case MODULE_CMD_FINI: 2210 #ifdef _MODULE 2211 error = config_fini_component(cfdriver_ioconf_dbcool, 2212 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool); 2213 sysctl_teardown(&dbcool_sysctl_clog); 2214 #endif 2215 return error; 2216 default: 2217 return ENOTTY; 2218 } 2219 } 2220
Indexes created Thu Aug 20 00:25:57 UTC 2026