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    Searched refs:ANY_EXTEND_VECTOR_INREG (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 739 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
748 ANY_EXTEND_VECTOR_INREG,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 110 /// Implement expansion for ANY_EXTEND_VECTOR_INREG.
436 case ISD::ANY_EXTEND_VECTOR_INREG:
742 case ISD::ANY_EXTEND_VECTOR_INREG:
1005 "ANY_EXTEND_VECTOR_INREG vector size mismatch");
1036 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
SelectionDAGDumper.cpp 337 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
LegalizeVectorTypes.cpp 67 case ISD::ANY_EXTEND_VECTOR_INREG:
418 case ISD::ANY_EXTEND_VECTOR_INREG:
960 case ISD::ANY_EXTEND_VECTOR_INREG:
2208 case ISD::ANY_EXTEND_VECTOR_INREG:
3082 case ISD::ANY_EXTEND_VECTOR_INREG:
3562 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp);
3689 case ISD::ANY_EXTEND_VECTOR_INREG:
3703 case ISD::ANY_EXTEND_VECTOR_INREG:
4660 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp);
TargetLowering.cpp 805 case ISD::ANY_EXTEND_VECTOR_INREG:
1897 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1935 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND;
1971 case ISD::ANY_EXTEND_VECTOR_INREG: {
1976 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG;
2776 case ISD::ANY_EXTEND_VECTOR_INREG:
2789 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
LegalizeIntegerTypes.cpp 117 case ISD::ANY_EXTEND_VECTOR_INREG:
4855 case ISD::ANY_EXTEND_VECTOR_INREG:
DAGCombiner.cpp 11846 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
20605 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT))
20607 DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG,
20631 if (Opcode != ISD::ANY_EXTEND_VECTOR_INREG &&
SelectionDAG.cpp 3282 case ISD::ANY_EXTEND_VECTOR_INREG: {
4931 case ISD::ANY_EXTEND_VECTOR_INREG:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLoweringHVX.cpp 129 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
162 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
1645 assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
2117 case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetLoweringBase.cpp 810 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 1041 case ISD::ANY_EXTEND_VECTOR_INREG: {
X86ISelLowering.cpp 2038 setTargetDAGCombine(ISD::ANY_EXTEND_VECTOR_INREG);
6339 case ISD::ANY_EXTEND_VECTOR_INREG:
6355 case ISD::ANY_EXTEND_VECTOR_INREG:
6356 return ISD::ANY_EXTEND_VECTOR_INREG;
7890 case ISD::ANY_EXTEND_VECTOR_INREG: {
7900 (ISD::ANY_EXTEND == Opcode || ISD::ANY_EXTEND_VECTOR_INREG == Opcode);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 5790 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&

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