Home | Sort by: relevance | last modified time | path |
/src/sys/arch/mips/atheros/include/ | |
ar9344reg.h | 125 #define AR9344_CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV __BITS(5,9) |
/src/sys/arch/mips/atheros/ | |
ar9344.c | 171 AR9344_CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV); |