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Searched refs:ARCHIP_DDR_BASE (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/atheros/
ar7100.c	132 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_0) = 0x10000000; 133 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_1) = 0x11000000; 134 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_2) = 0x12000000; 135 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_3) = 0x13000000; 136 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_4) = 0x14000000; 137 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_5) = 0x15000000; 138 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_6) = 0x16000000; 139 REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_7) = 0x07000000;
/src/sys/arch/mips/atheros/include/
ar9344reg.h	`39 #define ARCHIP_DDR_BASE 0x18000000 246 * DDR registers -- offset relative to ARCHIP_DDR_BASE 351 #define GETDDRREG(x) REGVAL((x) + ARCHIP_DDR_BASE) 352 #define PUTDDRREG(x,v) (REGVAL((x) + ARCHIP_DDR_BASE)) = (v)`

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