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    Searched refs:AR_IMR_S0 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_xmit.c 182 OS_REG_WRITE(ah, AR_IMR_S0,
ar5211reg.h 56 #define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */
ar5211_reset.c 499 OS_REG_WRITE(ah, AR_IMR_S0,
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212reg.h 53 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
ar5212_xmit.c 214 OS_REG_WRITE(ah, AR_IMR_S0,
  /src/sys/dev/ic/
athnreg.h 58 #define AR_IMR_S0 0x00a4
503 /* Bits for AR_IMR_S0. */
athn.c 1962 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);

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