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Searched refs:AR_IMR_S1 (Results 1 - 7 of 7) sorted by relevancy

/src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_xmit.c	`186 OS_REG_WRITE(ah, AR_IMR_S1,`
ar5211reg.h	`57 #define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */`
ar5211_reset.c	`502 OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0));`
/src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212reg.h	`54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */`
ar5212_xmit.c	`218 OS_REG_WRITE(ah, AR_IMR_S1,`
/src/sys/dev/ic/
athnreg.h	`59 #define AR_IMR_S1 0x00a8 507 /* Bits for AR_IMR_S1. */`
athn.c	`1964 AR_WRITE(sc, AR_IMR_S1, 0x00df0000);`

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