HomeSort by: relevance | last modified time | path
    Searched refs:AR_IMR_S2 (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_interrupts.c 183 * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
192 OS_REG_WRITE(ah, AR_IMR_S2,
193 (OS_REG_READ(ah, AR_IMR_S2) & ~AR_IMR_SR2_BCNMISC) | mask2);
ar5212reg.h 55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
ar5212_xmit.c 222 OS_REG_RMW_FIELD(ah, AR_IMR_S2,
ar5212_reset.c 563 OS_REG_WRITE(ah, AR_IMR_S2,
564 OS_REG_READ(ah, AR_IMR_S2)
  /src/sys/external/isc/atheros_hal/dist/ar5416/
ar5416_interrupts.c 242 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
250 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
ar5416_reset.c 590 OS_REG_WRITE(ah, AR_IMR_S2,
591 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312_reset.c 526 OS_REG_WRITE(ah, AR_IMR_S2,
527 OS_REG_READ(ah, AR_IMR_S2)
  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_reset.c 503 OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0));
516 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) |
ar5211_xmit.c 190 OS_REG_RMW_FIELD(ah, AR_IMR_S2,
ar5211reg.h 58 #define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */
  /src/sys/dev/ic/
athn.c 2120 mask2 = AR_READ(sc, AR_IMR_S2);
2124 AR_WRITE(sc, AR_IMR_S2, mask2);
2153 AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
2341 AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
athnreg.h 60 #define AR_IMR_S2 0x00ac
511 /* Bits for AR_IMR_S2. */

Completed in 33 milliseconds