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    Searched refs:ATOMIC_LOAD (Results 1 - 23 of 23) sorted by relevancy

  /src/external/bsd/libc++/dist/libcxxrt/src/
atomic.h 10 * ATOMIC_LOAD.
24 #define ATOMIC_LOAD(addr)\
27 #define ATOMIC_LOAD(addr)\
memory.cc 69 return ATOMIC_LOAD(&new_handl);
exception.cc 1522 return ATOMIC_LOAD(&unexpectedHandler);
1534 return ATOMIC_LOAD(&terminateHandler);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1098 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
1100 ATOMIC_LOAD,
SelectionDAGNodes.h 1382 N->getOpcode() == ISD::ATOMIC_LOAD ||
1399 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||
1439 N->getOpcode() == ISD::ATOMIC_LOAD ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 155 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
222 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
939 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
999 // Because of how we convert atomic_load and atomic_store to normal loads and
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 99 case ISD::ATOMIC_LOAD: return "AtomicLoad";
SelectionDAG.cpp 727 case ISD::ATOMIC_LOAD:
3557 case ISD::ATOMIC_LOAD: {
4161 case ISD::ATOMIC_LOAD: {
7099 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
LegalizeIntegerTypes.cpp 186 case ISD::ATOMIC_LOAD:
2105 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
LegalizeDAG.cpp 2748 case ISD::ATOMIC_LOAD: {
SelectionDAGBuilder.cpp 4700 SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRuntimeLibcallSignatures.cpp 419 Table[RTLIB::ATOMIC_LOAD] = unsupported;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1602 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1608 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
3065 case ISD::ATOMIC_LOAD:
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AtomicExpandPass.cpp 1516 RTLIB::ATOMIC_LOAD, RTLIB::ATOMIC_LOAD_1, RTLIB::ATOMIC_LOAD_2,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 240 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
SIISelLowering.cpp 829 setTargetDAGCombine(ISD::ATOMIC_LOAD);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp 86 case ISD::ATOMIC_LOAD:
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 189 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
191 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
251 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
4071 // Because of how we convert atomic_load and atomic_store to normal loads and
5431 case ISD::ATOMIC_LOAD:
5518 case ISD::ATOMIC_LOAD: {
7342 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
7463 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 816 Use->getOpcode() != ISD::ATOMIC_LOAD &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1324 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1327 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
9935 case ISD::ATOMIC_LOAD:
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 1279 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 513 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
    [all...]

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